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Searched refs:MXL_RV128 (Results 1 – 10 of 10) sorted by relevance

/qemu/target/riscv/
H A Dtranslate.c353 case MXL_RV128: in get_gpr()
363 assert(get_xl(ctx) == MXL_RV128); in get_gprh()
394 case MXL_RV128: in gen_set_gpr()
401 if (get_xl_max(ctx) == MXL_RV128) { in gen_set_gpr()
415 case MXL_RV128: in gen_set_gpri()
422 if (get_xl_max(ctx) == MXL_RV128) { in gen_set_gpri()
430 assert(get_ol(ctx) == MXL_RV128); in gen_set_gpr128()
797 if (get_xl(ctx) != MXL_RV128) { \
828 if (get_ol(ctx) == MXL_RV128) { in ex_rvc_shiftli()
840 if (get_ol(ctx) == MXL_RV128) { in ex_rvc_shiftri()
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H A Dgdbstub.c69 case MXL_RV128: in riscv_cpu_gdb_read_register()
91 case MXL_RV128: in riscv_cpu_gdb_write_register()
370 case MXL_RV128: in riscv_cpu_register_gdb_regs_for_features()
H A Ddebug.c85 case MXL_RV128: in extract_trigger_type()
144 case MXL_RV128: in build_tdata1()
192 case MXL_RV128: in tdata1_validate()
241 case MXL_RV128: in textra_validate()
270 case MXL_RV128: in textra_validate()
385 case MXL_RV128: in trigger_textra_match()
H A Dcpu.c820 case MXL_RV128: in riscv_cpu_disas_set_info()
1180 case MXL_RV128: in riscv_cpu_validate_misa_mxl()
1967 case MXL_RV128: in prop_marchid_set()
2615 case MXL_RV128: in riscv_gdb_arch_name()
2720 assert(def->misa_mxl_max <= MXL_RV128); in riscv_cpu_class_base_init()
3173 .misa_mxl_max = MXL_RV128,
H A Dmachine.c173 return mcc->def->misa_mxl_max == MXL_RV128; in rv128_needed()
H A Dcpu_bits.h589 MXL_RV128 = 3, enumerator
H A Dcsr.c1897 case MXL_RV128: in add_status_sd()
2075 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, in read_mstatus_i128()
2083 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); in read_misa_i128()
3861 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); in read_sstatus_i128()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvzacas.c.inc58 if (get_xl_max(ctx) == MXL_RV128) {
93 case MXL_RV128:
H A Dtrans_rvi.c.inc276 if (get_xl(ctx) == MXL_RV128) {
409 if (get_xl(ctx) == MXL_RV128) {
510 if (get_xl(ctx) == MXL_RV128) {
1049 if (xl < MXL_RV128) {
1089 if (get_xl(ctx) < MXL_RV128) {
1118 if (get_xl(ctx) < MXL_RV128) {
1140 if (xl < MXL_RV128) {
1179 if (get_xl(ctx) < MXL_RV128) {
1207 if (get_xl(ctx) < MXL_RV128) {
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1190 if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) { in riscv_tcg_cpu_realize()