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Searched refs:MSTATUS64_UXL (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h576 #define MSTATUS64_UXL 0x0000000300000000ULL macro
H A Dcpu.h730 xl = get_field(env->mstatus, MSTATUS64_UXL); in cpu_get_xl()
H A Dcpu.c704 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold()
709 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold()
713 MSTATUS64_UXL, env->misa_mxl); in riscv_cpu_reset_hold()
H A Dcpu_helper.c594 MSTATUS64_UXL | MSTATUS_VS; in riscv_cpu_swap_hypervisor_regs()
H A Dcsr.c2023 if ((val & MSTATUS64_UXL) != 0) { in write_mstatus()
2024 mask |= MSTATUS64_UXL; in write_mstatus()