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Searched refs:MSR_TGPR (Results 1 – 6 of 6) sorted by relevance

/qemu/target/ppc/
H A Dmachine.c21 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); in post_load_update_msr()
H A Dhelper_regs.c318 ((value ^ env->msr) & (1 << MSR_TGPR)))) { in hreg_store_msr()
H A Dexcp_helper.c623 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { in powerpc_excp_6xx()
624 new_msr |= (target_ulong)1 << MSR_TGPR; in powerpc_excp_6xx()
H A Dtcg-excp_helper.c496 msr &= ~(1ULL << MSR_TGPR); in do_rfi()
H A Dcpu.h445 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */ macro
495 FIELD(MSR, TGPR, MSR_TGPR, 1)
H A Dcpu_init.c2597 (1ull << MSR_TGPR) | in POWERPC_FAMILY()
2636 (1ull << MSR_TGPR) | in POWERPC_FAMILY()
3311 (1ull << MSR_TGPR) |
3351 (1ull << MSR_TGPR) |
3397 (1ull << MSR_TGPR) | in POWERPC_FAMILY()