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Searched refs:MSR_SE (Results 1 – 4 of 4) sorted by relevance

/qemu/target/ppc/
H A Dcpu_init.h41 (1ull << MSR_SE) | \
H A Dcpu_init.c2505 (1ull << MSR_SE) | in POWERPC_FAMILY()
2546 (1ull << MSR_SE) | in POWERPC_FAMILY()
2603 (1ull << MSR_SE) | in POWERPC_FAMILY()
2643 (1ull << MSR_SE) | in POWERPC_FAMILY()
3318 (1ull << MSR_SE) |
3358 (1ull << MSR_SE) |
3404 (1ull << MSR_SE) | in POWERPC_FAMILY()
3459 (1ull << MSR_SE) |
3505 (1ull << MSR_SE) |
3562 (1ull << MSR_SE) |
[all …]
H A Dhelper_regs.c161 QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); in hreg_compute_hflags_value()
162 msr_mask |= 1 << MSR_SE; in hreg_compute_hflags_value()
H A Dcpu.h453 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */ macro
503 FIELD(MSR, SE, MSR_SE, 1)