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Searched refs:MSR_ISF (Results 1 – 1 of 1) sorted by relevance

/qemu/target/ppc/
H A Dcpu.h429 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */ macro
473 FIELD(MSR, ISF, MSR_ISF, 1)