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Searched refs:MSR_HV (Results 1 – 6 of 6) sorted by relevance

/qemu/target/ppc/
H A Dcpu_init.h33 (1ull << MSR_HV) | \
H A Dhelper_regs.c70 hv = !!(env->msr & (1ull << MSR_HV)); in hreg_check_bhrb_enable()
191 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { in hreg_compute_hflags_value()
230 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; in hreg_compute_hflags_value()
H A Dtcg-excp_helper.c331 !(env->msr & ((target_ulong)1 << MSR_HV))); in ppc_cpu_debug_check_breakpoint()
334 (env->msr & ((target_ulong)1 << MSR_HV))); in ppc_cpu_debug_check_breakpoint()
369 } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { in ppc_cpu_debug_check_watchpoint()
H A Dcpu.h430 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */ macro
475 FIELD(MSR, HV, MSR_HV, 1)
653 #define MSR_HVB (1ULL << MSR_HV)
H A Dtranslate.c4230 (1ULL << MSR_HV)); in gen_mtmsrd()
H A Dcpu_init.c6378 (1ull << MSR_HV) | in POWERPC_FAMILY()