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Searched refs:MSR_DWE (Results 1 – 2 of 2) sorted by relevance

/qemu/target/ppc/
H A Dcpu_init.c2191 (1ull << MSR_DWE) |
2263 (1ull << MSR_DWE) |
2302 (1ull << MSR_DWE) |
2354 (1ull << MSR_DWE) |
2424 (1ull << MSR_DWE) |
2463 (1ull << MSR_DWE) |
2789 (1ull << MSR_DWE) | in POWERPC_FAMILY()
3072 (1ull << MSR_DWE) | in POWERPC_FAMILY()
3116 (1ull << MSR_DWE) | in POWERPC_FAMILY()
H A Dcpu.h454 #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */ macro
504 FIELD(MSR, DWE, MSR_DWE, 1)