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Searched refs:MSA (Results 1 – 7 of 7) sorted by relevance

/qemu/disas/
H A Dmips.c1240 #define MSA INSN_MSA macro
1425 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1429 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1432 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1433 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/qemu/tests/tcg/mips/user/ase/msa/
H A DREADME2 mips64el MSA-enabled CPU (I6400, I6500), using an appropriate MIPS toolchain.
14 MSA tests:
/qemu/target/s390x/
H A Dcpu_features.c247 FEAT_GROUP_INIT("msa", MSA, "Message-security-assist facility"),
H A Dgen-features.c1015 FEAT_GROUP_INITIALIZER(MSA),
H A Dcpu_features_def.h.inc39 DEF_FEAT(MSA, "msa-base", STFL, 17, "Message-security-assist facility (excluding subfunctions)")
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc1005 /* MSA Instructions */
1006 D(0xb91e, KMAC, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMAC)
1012 D(0xb92e, KM, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KM)
1013 D(0xb92f, KMC, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMC)
1016 D(0xb93e, KIMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KIMD)
1017 D(0xb93f, KLMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KLMD)
/qemu/target/mips/tcg/
H A Dmsa_helper.h.inc2 * MIPS SIMD Architecture Module (MSA) helpers for QEMU.