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Searched refs:MMQReg (Results 1 – 7 of 7) sorted by relevance

/qemu/target/hexagon/
H A Dcpu.h99 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
100 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
107 MMQReg qtmp QEMU_ALIGNED(16);
H A Dgen_tcg_hvx.h401 sizeof(MMQReg), sizeof(MMQReg))
405 sizeof(MMQReg), sizeof(MMQReg))
409 sizeof(MMQReg), sizeof(MMQReg))
413 sizeof(MMQReg), sizeof(MMQReg))
417 sizeof(MMQReg), sizeof(MMQReg))
421 sizeof(MMQReg), sizeof(MMQReg))
460 OP(MO_64, QxV_off, QxV_off, qoff, sizeof(MMQReg), sizeof(MMQReg)); \
H A Dhex_arch_types.h40 typedef MMQReg mmqret_t;
H A Dgenptr.c1263 tcg_gen_gvec_dup_imm(MO_64, maskoff, sizeof(MMQReg), sizeof(MMQReg), ~0LL); in gen_vreg_store()
1280 tcg_gen_gvec_mov(MO_64, maskoff, bitsoff, sizeof(MMQReg), sizeof(MMQReg)); in gen_vreg_masked_store()
1283 sizeof(MMQReg), sizeof(MMQReg)); in gen_vreg_masked_store()
H A Dtranslate.c772 size_t size = sizeof(MMQReg); in gen_commit_hvx()
/qemu/target/hexagon/mmvec/
H A Dmacros.h41 #define QeV (*(MMQReg *restrict)(QeV_void))
42 #define QdV (*(MMQReg *restrict)(QdV_void))
43 #define QsV (*(MMQReg *restrict)(QsV_void))
44 #define QtV (*(MMQReg *restrict)(QtV_void))
45 #define QuV (*(MMQReg *restrict)(QuV_void))
46 #define QvV (*(MMQReg *restrict)(QvV_void))
47 #define QxV (*(MMQReg *restrict)(QxV_void))
63 MMQReg _ret; \
H A Dmmvec.h64 } MMQReg; typedef