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Searched refs:MIP_SGEIP (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h770 #define MIP_SGEIP (1 << IRQ_S_GEXT) macro
791 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
H A Dcpu.c720 env->miclaim = MIP_SGEIP; in riscv_cpu_reset_hold()
1068 riscv_cpu_update_mip(env, MIP_SGEIP, in riscv_cpu_set_irq()
H A Dcpu_helper.c438 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); in riscv_cpu_mirq_pending()
H A Dcsr.c4853 riscv_cpu_update_mip(env, MIP_SGEIP, in write_hgeie()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1208 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; in riscv_tcg_cpu_realize()