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Searched refs:MHPMEVENT_BIT_UINH (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h1062 #define MHPMEVENT_BIT_UINH BIT_ULL(60) macro
1071 MHPMEVENT_BIT_UINH | \
H A Dpmu.c162 (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) { in riscv_pmu_incr_ctr_rv64()
H A Dcsr.c1182 inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0; in write_mhpmevent()