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Searched refs:ISELECT_IMSIC_EIDELIVERY (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h976 #define ISELECT_IMSIC_EIDELIVERY 0x70 macro
982 #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY
H A Dcsr.c2648 env->siselect >= ISELECT_IMSIC_EIDELIVERY && in rmw_xireg_aia()
/qemu/hw/intc/
H A Driscv_imsic.c235 case ISELECT_IMSIC_EIDELIVERY: in riscv_imsic_rmw()