Home
last modified time | relevance | path

Searched refs:ISA_MIPS4 (Results 1 – 4 of 4) sorted by relevance

/qemu/target/mips/
H A Dmips-defs.h17 #define ISA_MIPS4 0x0000000000000008ULL macro
60 #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
H A Dinternal.h390 } else if (env->insn_flags & ISA_MIPS4) { in compute_hflags()
/qemu/disas/
H A Dmips.c621 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) macro
622 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
3916 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3918 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3920 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3924 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3926 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3928 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3930 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3932 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
/qemu/target/mips/tcg/
H A Dtranslate.c8686 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); in gen_compute_branch1()
13139 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | in decode_opc_special_legacy()
13152 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); in decode_opc_special_legacy()
14668 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); in decode_opc_legacy()
14877 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); in decode_opc_legacy()
14881 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); in decode_opc_legacy()
14899 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); in decode_opc_legacy()