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Searched refs:HW (Results 1 – 24 of 24) sorted by relevance

/qemu/audio/
H A Daudio_template.h29 #define HW HWVoiceOut macro
34 #define HW HWVoiceIn macro
78 static void glue (audio_pcm_hw_free_resources_, TYPE) (HW *hw) in glue()
86 static void glue(audio_pcm_hw_alloc_resources_, TYPE)(HW *hw) in glue()
117 HW *hw = sw->hw; in glue()
160 HW *hw, in glue()
211 static void glue (audio_pcm_hw_add_sw_, TYPE) (HW *hw, SW *sw) in glue()
221 static void glue (audio_pcm_hw_gc_, TYPE) (HW **hwp) in glue()
223 HW *hw = *hwp; in glue()
239 static HW *glue(audio_pcm_hw_find_any_, TYPE)(AudioState *s, HW *hw) in glue()
[all …]
/qemu/target/hexagon/imported/
H A Dbranch.idef208 /* HW Loop instructions */
211 Q6INSN(J2_loop0r,"loop0(#r7:2,Rs32)",ATTRIBS(),"Initialize HW loop 0",
217 Q6INSN(J2_loop1r,"loop1(#r7:2,Rs32)",ATTRIBS(),"Initialize HW loop 1",
222 Q6INSN(J2_loop0i,"loop0(#r7:2,#U10)",ATTRIBS(),"Initialize HW loop 0",
228 Q6INSN(J2_loop1i,"loop1(#r7:2,#U10)",ATTRIBS(),"Initialize HW loop 1",
234 Q6INSN(J2_ploop1sr,"p3=sp1loop0(#r7:2,Rs32)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
240 Q6INSN(J2_ploop1si,"p3=sp1loop0(#r7:2,#U10)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
247 Q6INSN(J2_ploop2sr,"p3=sp2loop0(#r7:2,Rs32)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
253 Q6INSN(J2_ploop2si,"p3=sp2loop0(#r7:2,#U10)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
260 Q6INSN(J2_ploop3sr,"p3=sp3loop0(#r7:2,Rs32)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
[all …]
/qemu/docs/
H A Dqemupciserial.inf50 [ComPort_inst1.HW]
53 [ComPort_inst2.HW]
56 [ComPort_inst4.HW]
H A Digd-assign.txt255 Non- | | "real" one in HW
/qemu/docs/specs/
H A Dacpi_hw_reduced_hotplug.rst5 The ACPI *Generic Event Device* (GED) is a HW reduced platform
11 GED allows HW reduced platforms to handle interrupts in ACPI ASL
H A Dppc-xive.rst101 HW events | | | | | |
118 the processor HW threads. It maintains the interrupt context state of
125 HW threads:
H A Dppc-spapr-xive.rst7 virtualization features which enables the HW to deliver interrupts
H A Dppc-spapr-numa.rst31 | HW module 1 (MOD1)
/qemu/docs/system/i386/
H A Dxenpvh.rst5 on HW virtualization features, emulation models and paravirtualization.
6 PVH is a mode that uses HW virtualization features (like HVM) but tries
/qemu/docs/devel/
H A Dindex-tcg.rst8 are only implementing things for HW accelerated hypervisors.
H A Dmulti-process.rst36 often accelerated by HW virtualization features such as Intel's VT
37 extensions. Finally, it provides IO services to the VM by emulating HW
121 VMs are often run using HW virtualization features via the KVM kernel
123 instructions by running the guest in a virtual HW mode. When the guest
124 executes instructions that cannot be executed by virtual HW mode,
354 device, the VM will exit HW virtualization mode and return to QEMU,
530 PCI MSI/X interrupts are implemented in HW as DMA writes to a
H A Dtcg-plugins.rst132 than in real HW due to the inefficiencies of emulation giving less
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc41 C(0xb9c8, AHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, adds32)
42 C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32)
51 C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32)
71 C(0xb9ca, ALHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, addu32)
72 C(0xb9da, ALHHLR, RRF_a, HW, r2_sr32, r3_32u, new, r1_32h, add, addu32)
82 C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu32)
83 C(0xcc0b, ALSIHN, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, 0)
138 C(0xcc06, BRCTH, RIL_b, HW, 0, 0, 0, 0, bcth, 0)
205 C(0xb9cd, CHHR, RRE, HW, r1_sr32, r2_sr32, 0, 0, 0, cmps32)
206 C(0xb9dd, CHLR, RRE, HW, r1_sr32, r2_o, 0, 0, 0, cmps32)
[all …]
/qemu/hw/intc/
H A Dgic_internal.h119 FIELD(GICH_LR0, HW, 31, 1)
142 #define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW))
/qemu/docs/system/devices/
H A Divshmem-flat.rst13 notification via HW interrupts and Inter-VM shared memory. This allows the
/qemu/target/hexagon/
H A Dattribs_def.h.inc143 DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "")
144 DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "")
/qemu/target/arm/tcg/
H A Dsve_helper.c1047 #define DO_ZZZ_TB(NAME, TYPEW, TYPEN, HW, HN, OP) \ argument
1056 *(TYPEW *)(vd + HW(i)) = OP(nn, mm); \
1117 #define DO_ZZZ_WTB(NAME, TYPEW, TYPEN, HW, HN, OP) \ in DO_ZZZ_TB() argument
1123 TYPEW nn = *(TYPEW *)(vn + HW(i)); \ in DO_ZZZ_TB()
1125 *(TYPEW *)(vd + HW(i)) = OP(nn, mm); \ in DO_ZZZ_TB()
1167 #define DO_ZZZW_ACC(NAME, TYPEW, TYPEN, HW, HN, OP) \ argument
1175 TYPEW aa = *(TYPEW *)(va + HW(i)); \
1176 *(TYPEW *)(vd + HW(i)) = OP(nn, mm) + aa; \
1298 #define DO_SQDMLAL(NAME, TYPEW, TYPEN, HW, HN, DMUL_OP, SUM_OP) \ argument
1307 TYPEW aa = *(TYPEW *)(va + HW(i)); \
[all …]
/qemu/docs/devel/migration/
H A Duadk-compression.rst59 | HW Accelerators |
/qemu/docs/system/arm/
H A Daspeed.rst163 device. It is slower to start but closer to what HW does. Using the
/qemu/docs/about/
H A Ddeprecated.rst511 string) to a guest. Calxeda HW has been ewasted now and there is no point
H A Demulation.rst628 - Instead break down the accesses based on the offset into the HW
/qemu/hw/net/
H A Dtrace-events8 allwinner_sun8i_emac_reset(void) "HW reset"
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc758 Note that SHIFT is a full shift count, not the 2 bit HW field. */
/qemu/
H A Dmeson.build1814 # Version 3.6.14 is needed to get HW accelerated XTS