Searched refs:GPR (Results 1 – 5 of 5) sorted by relevance
| /qemu/disas/ |
| H A D | nanomips.c | 405 static const char *GPR(uint64 reg, Dis_info *info) in GPR() function
435 reg_list[counter + 1] = (char *)GPR(this_rt, info); in save_restore_list()
1479 const char *rt = GPR(rt_value, info); in ABSQ_S_PH()
1480 const char *rs = GPR(rs_value, info); in ABSQ_S_PH()
1501 const char *rt = GPR(rt_value, info); in ABSQ_S_QB()
1502 const char *rs = GPR(rs_value, info); in ABSQ_S_QB()
1523 const char *rt = GPR(rt_value, info); in ABSQ_S_W()
1524 const char *rs = GPR(rs_value, info); in ABSQ_S_W()
1545 const char *rs = GPR(rs_value, info); in ACLR()
1567 const char *rd = GPR(rd_value, info); in ADD()
[all …]
|
| /qemu/target/hexagon/ |
| H A D | README | 208 runtime information for each thread and contains stuff like the GPR and
|
| /qemu/target/hexagon/imported/ |
| H A D | compare.idef | 56 /* Compare and put result in GPR */
|
| /qemu/target/i386/tcg/ |
| H A D | decode-new.c.inc | 2018 case X86_TYPE_B: /* VEX.vvvv selects a GPR */
2054 case X86_TYPE_G: /* REG in the modrm byte selects a GPR */
|
| /qemu/tcg/riscv/ |
| H A D | tcg-target.c.inc | 674 * Vector registers uses the same 5 lower bits as GPR registers,
|