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Searched refs:FPCR_DYN_SHIFT (Results 1 – 3 of 3) sorted by relevance

/qemu/tests/tcg/alpha/
H A Dtest-cvttq.c7 #define FPCR_DYN_SHIFT 58 macro
8 #define FPCR_DYN_CHOPPED (0UL << FPCR_DYN_SHIFT)
9 #define FPCR_DYN_MINUS (1UL << FPCR_DYN_SHIFT)
10 #define FPCR_DYN_NORMAL (2UL << FPCR_DYN_SHIFT)
11 #define FPCR_DYN_PLUS (3UL << FPCR_DYN_SHIFT)
12 #define FPCR_DYN_MASK (3UL << FPCR_DYN_SHIFT)
/qemu/target/alpha/
H A Dcpu.h133 #define FPCR_DYN_SHIFT (58 - 32) macro
134 #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT)
135 #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT)
136 #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT)
137 #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT)
138 #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT)
H A Dhelper.c43 [FPCR_DYN_NORMAL >> FPCR_DYN_SHIFT] = float_round_nearest_even, in cpu_alpha_store_fpcr()
44 [FPCR_DYN_CHOPPED >> FPCR_DYN_SHIFT] = float_round_to_zero, in cpu_alpha_store_fpcr()
45 [FPCR_DYN_MINUS >> FPCR_DYN_SHIFT] = float_round_down, in cpu_alpha_store_fpcr()
46 [FPCR_DYN_PLUS >> FPCR_DYN_SHIFT] = float_round_up, in cpu_alpha_store_fpcr()
81 env->fpcr_dyn_round = rm_map[(fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIFT]; in cpu_alpha_store_fpcr()