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Searched refs:DIV (Results 1 – 11 of 11) sorted by relevance

/qemu/target/sparc/
H A Dcpu-feature.h.inc3 FEATURE(DIV)
H A Dtranslate.c3778 TRANS(UDIVcc, DIV, do_arith, a, NULL, NULL, gen_op_udivcc) in TRANS()
3779 TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL, gen_op_sdivcc) in TRANS()
/qemu/target/rx/
H A Dinsns.decode222 # DIV #imm, rd
224 # DIV dsp[rs].ub, rd
225 # DIV rs, rd
227 # DIV dsp[rs], rd
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc3334 #define DIVU32(NAME, DIV) \
3340 DIV(t, a, b); \
3343 #define DIVS32(NAME, DIV) \
3355 DIV(t, a, b); \
3358 #define DIVU64(NAME, DIV) \
3364 DIV(t, a, b); \
3367 #define DIVS64(NAME, DIV) \
3379 DIV(t, a, b); \
/qemu/hw/misc/
H A Dbcm2835_cprman.c183 div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); in pll_channel_update()
/qemu/include/hw/misc/
H A Dbcm2835_cprman_internals.h114 FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8)
/qemu/target/mips/tcg/
H A Dmicromips_translate.c.inc258 DIV = 0xa,
1138 case DIV:
1768 case LWXS: /* DIV */
1770 /* DIV */
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc4051 #define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \
4054 if (int_ext_check(s, a, DIV)) { \
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc1511 [0x06] = X86_OP_ENTRYr(DIV, E,b),
1520 [0x0e] = X86_OP_ENTRYr(DIV, E,v),
/qemu/disas/
H A Dnanomips.c5475 static char *DIV(uint64 instruction, Dis_info *info) in DIV() function
16405 0xfc0003ff, 0x20000118, &DIV , 0,
/qemu/tests/tcg/i386/
H A Dx86.csv561 "DIV r/m8","DIVB r/m8","divb r/m8","F6 /6","V","V","","","r","Y","8"
562 "DIV r/m8","DIVB r/m8","divb r/m8","REX F6 /6","N.E.","V","","pseudo64","w","Y","8"
563 "DIV r/m32","DIVL r/m32","divl r/m32","F7 /6","V","V","","operand32","r","Y","32"
566 "DIV r/m64","DIVQ r/m64","divq r/m64","REX.W F7 /6","N.S.","V","","","r","Y","64"
569 "DIV r/m16","DIVW r/m16","divw r/m16","F7 /6","V","V","","operand16","r","Y","16"