| /qemu/tests/qemu-iotests/ |
| H A D | 142.out | 38 Cache mode: writeback, direct
39 Cache mode: writeback, direct
40 Cache mode: writeback, direct
41 Cache mode: writeback, direct
42 Cache mode: writeback, direct
45 Cache mode: writeback
46 Cache mode: writeback
47 Cache mode: writeback, direct
48 Cache mode: writeback
49 Cache mode: writeback
[all …]
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| H A D | 157.out | 7 Cache mode: writeback
9 Cache mode: writeback
11 Cache mode: writeback
13 Cache mode: writethrough
15 Cache mode: writethrough
17 Cache mode: writethrough
19 Cache mode: writeback
21 Cache mode: writethrough
|
| H A D | 186.out | 62 Cache mode: writeback
70 Cache mode: writeback
78 Cache mode: writeback
86 Cache mode: writeback
94 Cache mode: writeback
102 Cache mode: writeback
111 Cache mode: writeback
120 Cache mode: writeback
129 Cache mode: writeback
138 Cache mode: writeback
[all …]
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| H A D | 172.out | 66 Cache mode: writeback
116 Cache mode: writeback
170 Cache mode: writeback
175 Cache mode: writeback
254 Cache mode: writeback
304 Cache mode: writeback
358 Cache mode: writeback
363 Cache mode: writeback
402 Cache mode: writeback
438 Cache mode: writeback
[all …]
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| H A D | 051.out | 87 Cache mode: writeback
150 === Cache modes ===
180 Cache mode: writeback
185 Cache mode: writeback
188 Cache mode: writeback, ignore flushes
192 Cache mode: writeback, ignore flushes
200 Cache mode: writethrough
205 Cache mode: writeback
208 Cache mode: writeback, ignore flushes
212 Cache mode: writeback, ignore flushes
[all …]
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| H A D | 051.pc.out | 87 Cache mode: writeback
230 === Cache modes ===
260 Cache mode: writeback
265 Cache mode: writeback
268 Cache mode: writeback, ignore flushes
272 Cache mode: writeback, ignore flushes
280 Cache mode: writethrough
285 Cache mode: writeback
288 Cache mode: writeback, ignore flushes
292 Cache mode: writeback, ignore flushes
[all …]
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| H A D | 137.out | 28 qemu-io: Cache clean interval too big
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| H A D | 051 | 242 echo === Cache modes ===
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| /qemu/contrib/plugins/ |
| H A D | cache.c | 81 } Cache; typedef
92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
95 void (*metadata_init)(Cache *cache);
96 void (*metadata_destroy)(Cache *cache);
99 static Cache **l1_dcaches, **l1_icaches;
102 static Cache **l2_ucaches;
140 static void lru_priorities_init(Cache *cache) in lru_priorities_init()
150 static void lru_update_blk(Cache *cache, int set_idx, int blk_idx) in lru_update_blk()
157 static int lru_get_lru_block(Cache *cache, int set_idx) in lru_get_lru_block()
[all …]
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| /qemu/target/hexagon/imported/ |
| H A D | system.idef | 36 Q6INSN(Y2_icinva,"icinva(Rs32)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",…
43 Q6INSN(Y2_dcfetchbo,"dcfetch(Rs32+#u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Pr…
47 Q6INSN(Y2_dccleana,"dccleana(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Add…
48 Q6INSN(Y2_dccleaninva,"dccleaninva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Cle…
49 Q6INSN(Y2_dcinva,"dcinva(Rs32)",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Ad…
52 Q6INSN(Y4_l2fetch,"l2fetch(Rs32,Rt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
62 Q6INSN(Y5_l2fetch,"l2fetch(Rs32,Rtt32)",ATTRIBS(A_RESTRICT_SLOT0ONLY),"L2 Cache Prefetch",
|
| H A D | macros.def | 1580 /* Cache Management */
|
| /qemu/util/ |
| H A D | cacheflush.c | 53 && buf[i].Cache.Level == 1) { in sys_cache_info()
54 switch (buf[i].Cache.Type) { in sys_cache_info()
56 *isize = *dsize = buf[i].Cache.LineSize; in sys_cache_info()
59 *isize = buf[i].Cache.LineSize; in sys_cache_info()
62 *dsize = buf[i].Cache.LineSize; in sys_cache_info()
|
| /qemu/qapi/ |
| H A D | machine-common.json | 86 # Cache information for SMP system.
88 # @cache: Cache name, which is the combination of cache level
91 # @topology: Cache topology level. It accepts the CPU topology
|
| H A D | machine.json | 756 # Cache associativity in the Memory Side Cache Information Structure
767 # @complex: Complex Cache Indexing (implementation specific)
777 # Cache write policy in the Memory Side Cache Information Structure of
|
| H A D | block-core.json | 449 # Cache mode information for a block device
|
| /qemu/docs/system/arm/ |
| H A D | emulation.rst | 33 - FEAT_CSV2 (Cache speculation variant 2)
34 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
35 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
36 - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
37 - FEAT_CSV2_3 (Cache speculation variant 2, version 3)
38 - FEAT_CSV3 (Cache speculation variant 3)
|
| /qemu/docs/ |
| H A D | xbzrle.txt | 20 Cache size can be changed before and during migration.
74 Cache update strategy
|
| H A D | qcow2-cache.txt | 114 Cache sizes can be configured using the -drive option in the
|
| /qemu/target/microblaze/ |
| H A D | insns.decode | 251 # Cache operations have no effect in qemu: discard the arguments.
|
| /qemu/docs/specs/ |
| H A D | riscv-iommu.rst | 79 - "ioatc-limit": size of the Address Translation Cache (default to 2Mb)
|
| H A D | rocker.rst | 59 0xC 1 Cache line size
|
| /qemu/docs/about/ |
| H A D | emulation.rst | 694 Cache Modelling
699 Cache modelling plugin that measures the performance of a given L1 cache
727 .. list-table:: Cache modelling arguments
|
| /qemu/docs/system/devices/ |
| H A D | cxl.rst | 40 * Cache operations. The are mostly irrelevant to QEMU emulation as
|
| /qemu/docs/devel/testing/ |
| H A D | main.rst | 221 Cache mode can be selected with the "-c" option, which may help reveal bugs
|
| /qemu/tests/functional/acpi-bits/bits-tests/ |
| H A D | smbios.py2 | 1112 0x07: "Cache memory"
|