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Searched refs:CTRTARGET_MISP (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h944 #define CTRTARGET_MISP BIT(0) macro
H A Dcpu_helper.c1023 env->ctr_dst[head] = dst & ~CTRTARGET_MISP; in riscv_ctr_add_entry()