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Searched refs:CSR_TINFO (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h403 #define CSR_TINFO 0x7a4 macro
H A Dcsr.c6136 [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },