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Searched refs:CSR_MSTATEEN2 (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h348 #define CSR_MSTATEEN2 0x30E macro
H A Dcsr.c5888 [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen,