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Searched refs:CSR_MIP (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h170 #define CSR_MIP 0x344 macro
H A Dcsr.c3782 ret = rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); in rmw_mvip64()
5829 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
H A Dcpu.c541 CSR_MIP, in riscv_cpu_dump_state()