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Searched refs:CS (Results 1 – 16 of 16) sorted by relevance

/qemu/hw/ssi/
H A Dtrace-events3 aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"P…
4 aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" P…
5 aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
6 aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" …
11 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
17 npcm7xx_fiu_select(const char *id, int cs) "%s select CS%d"
18 npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
44 pnv_spi_shifter_stating(void) "pull CS line low"
45 pnv_spi_shifter_done(void) "pull the CS line high"
H A Dxilinx_spips.c59 #define CS (0xF << 10) macro
291 int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); in xilinx_spips_update_cs_lines()
/qemu/docs/specs/
H A Dsev-guest-firmware.rst95 * CS segment base [31:16]
97 A hypervisor reads the CS segment base and IP value. The CS segment
98 base value represents the high order 16-bits of the CS segment base, so
99 the hypervisor must left shift the value of the CS segment base by 16
100 bits to form the full CS segment base for the CS segment register. It
/qemu/target/i386/hvf/
H A Dx86_descr.c39 VMX_SEGMENT_FIELD(CS),
/qemu/target/hexagon/
H A Dgen_tcg.h71 gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, CS); \
78 gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
115 gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
429 gen_helper_fcircadd(RxV, RxV, ireg, MuV, CS); \
H A Dop_helper.c149 int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, int32_t M, int32_t CS) in HELPER()
158 start_addr = CS; in HELPER()
H A Dmacros.h463 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, CS); \
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1382 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_ADD); /* for CS */
1398 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_ADD); /* for CS */
1860 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_SUB); /* for CS */
1873 tcg_out_arithi(s, a0, TCG_REG_T1, 1, ARITH_SUB); /* for CS */
/qemu/docs/devel/
H A Dtcg.rst37 Program Counter (PC) and other CPU state information (such as the CS
/qemu/fpu/
H A Dsoftfloat-specialize.c.inc30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
/qemu/include/block/
H A Dufs.h66 FIELD(CAP, CS, 28, 1)
/qemu/target/hexagon/imported/
H A Dmacros.def381 fREAD_CSREG, /* read CS register */
/qemu/hw/ufs/
H A Dufs.c1702 cap = FIELD_DP32(cap, CAP, CS, 0); in ufs_init_hc()
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc273 D(0xba00, CS, RS_a, Z, r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL)
/qemu/target/i386/tcg/
H A Ddecode-new.c.inc1725 [0x0E] = X86_OP_ENTRYr(PUSH, CS, w, chk(i64)),
/qemu/tests/tcg/i386/
H A Dx86.csv1683 "PUSH CS","PUSHW/PUSHL/PUSHQ CS","pushw/pushl/pushq CS","0E","V","N.S.","","","r","Y",""