| /qemu/include/block/ |
| H A D | ufs.h | 58 REG32(CAP, offsetof(UfsReg, cap))
59 FIELD(CAP, NUTRS, 0, 5)
60 FIELD(CAP, RTT, 8, 8)
61 FIELD(CAP, NUTMRS, 16, 3)
62 FIELD(CAP, AUTOH8, 23, 1)
63 FIELD(CAP, 64AS, 24, 1)
64 FIELD(CAP, OODDS, 25, 1)
65 FIELD(CAP, UICDMETMS, 26, 1)
66 FIELD(CAP, CS, 28, 1)
67 FIELD(CAP, LSDBS, 29, 1)
[all …]
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| /qemu/include/system/ |
| H A D | kvm.h | 172 #define KVM_CAP_INFO(CAP) { "KVM_CAP_" stringify(CAP), KVM_CAP_##CAP }
171 KVM_CAP_INFO(CAP) global() argument
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| /qemu/hw/ufs/ |
| H A D | ufs.c | 98 if (!FIELD_EX32(u->reg.cap, CAP, 64AS) && (hi >> 32)) { in ufs_addr_read()
113 if (!FIELD_EX32(u->reg.cap, CAP, 64AS) && (hi >> 32)) { in ufs_addr_write()
1695 cap = FIELD_DP32(cap, CAP, NUTRS, (u->params.nutrs - 1)); in ufs_init_hc()
1696 cap = FIELD_DP32(cap, CAP, RTT, 2); in ufs_init_hc()
1697 cap = FIELD_DP32(cap, CAP, NUTMRS, (u->params.nutmrs - 1)); in ufs_init_hc()
1698 cap = FIELD_DP32(cap, CAP, AUTOH8, 0); in ufs_init_hc()
1699 cap = FIELD_DP32(cap, CAP, 64AS, 1); in ufs_init_hc()
1700 cap = FIELD_DP32(cap, CAP, OODDS, 0); in ufs_init_hc()
1701 cap = FIELD_DP32(cap, CAP, UICDMETMS, 0); in ufs_init_hc()
1702 cap = FIELD_DP32(cap, CAP, CS, 0); in ufs_init_hc()
[all …]
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| /qemu/tests/qtest/ |
| H A D | ufs-test.c | 398 ufs->support_mcq = FIELD_EX32(cap, CAP, MCQS); in ufs_init()
465 nutrs = FIELD_EX32(cap, CAP, NUTRS) + 1; in ufs_init()
553 g_assert_cmpuint(FIELD_EX32(cap, CAP, NUTRS), ==, 31); in ufstest_reg_read()
554 g_assert_cmpuint(FIELD_EX32(cap, CAP, NUTMRS), ==, 7); in ufstest_reg_read()
555 g_assert_cmpuint(FIELD_EX32(cap, CAP, 64AS), ==, 1); in ufstest_reg_read()
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| /qemu/rust/hw/timer/hpet/src/ |
| H A D | device.rs | 121 CAP = 0, enumerator
803 Global(CAP) => self.capability.get(), /* including HPET_PERIOD 0x004 */ in read()
830 Global(CAP) => {} // General Capabilities and ID Register: Read Only in write()
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| /qemu/hw/vfio/ |
| H A D | trace-events | 29 vfio_msi_setup(const char *name, int pos) "%s PCI MSI CAP @0x%x"
30 … int table_bar, uint64_t offset, int entries, bool noresize) "%s PCI MSI-X CAP @0x%x, BAR %d, offs…
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| /qemu/docs/specs/ |
| H A D | ppc-xive.rst | 25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
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| /qemu/hw/nvme/ |
| H A D | trace-events | 201 pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO but CAP.NSSRS is zero…
202 pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset but CAP.NSSRS is zero (…
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| /qemu/docs/system/devices/ |
| H A D | nvme.rst | 226 the minimum memory page size (CAP.MPSMIN). The default value (``0``)
|