Searched refs:ubwc_swizzle (Results 1 – 6 of 6) sorted by relevance
18 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |27 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |41 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,50 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |60 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |69 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |79 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |88 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |98 .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |106 .ubwc_swizzle [all...]
19 * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.25 u32 ubwc_swizzle; member 69 if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1)) in qcom_ubwc_get_ubwc_mode()
173 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | in msm_mdss_setup_ubwc_dec_20() 188 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | in msm_mdss_setup_ubwc_dec_30() 206 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | in msm_mdss_setup_ubwc_dec_40() 232 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | in msm_mdss_setup_ubwc_dec_50()
283 fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | in dpu_hw_sspp_setup_format() 290 fast_clear | (ctx->ubwc->ubwc_swizzle) | in dpu_hw_sspp_setup_format() 295 BIT(30) | (ctx->ubwc->ubwc_swizzle) | in dpu_hw_sspp_setup_format()
620 cfg->ubwc_swizzle = 0x6; in a6xx_calc_ubwc_config() 625 cfg->ubwc_swizzle = 0x7; in a6xx_calc_ubwc_config() 655 cfg->ubwc_swizzle = 0x4; in a6xx_calc_ubwc_config() 668 if (cfg->ubwc_swizzle != common_cfg->ubwc_swizzle) in a6xx_calc_ubwc_config() 669 DRM_WARN_ONCE("Inconclusive ubwc_swizzle value: %u (GPU) vs %u (UBWC_CFG)\n", in a6xx_calc_ubwc_config() 670 cfg->ubwc_swizzle, common_cfg->ubwc_swizzle); in a6xx_calc_ubwc_config() 689 u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2); in a6xx_set_ubwc_config()
444 *value = adreno_gpu->ubwc_config->ubwc_swizzle; in adreno_get_param()