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Searched refs:sw_pll_48m_to_26m (Results 1 – 1 of 1) sorted by relevance

/linux/drivers/phy/mediatek/
H A Dphy-mtk-tphy.c281 * @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from
292 bool sw_pll_48m_to_26m; member
808 if (!tphy->pdata->sw_pll_48m_to_26m) in u2_phy_pll_26m_set()
1549 .sw_pll_48m_to_26m = true,