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Searched refs:skl (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c191 * Some skl systems, pre-release machines in particular, in skl_sagv_enable()
222 * Some skl systems, pre-release machines in particular, in skl_sagv_disable()
321 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
343 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
366 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
580 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; in skl_crtc_allocate_ddb()
581 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; in skl_crtc_allocate_ddb()
1429 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); in skl_crtc_allocate_plane_ddb()
1430 memset(crtc_state->wm.skl in skl_crtc_allocate_plane_ddb()
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H A Dintel_plane.c471 * And let's do this for all skl+ so that we can eg. change the in intel_plane_do_async_flip()
651 * flip (see {i9xx,skl}_plane_update_arm()). The in intel_plane_atomic_calc_changes()
815 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
817 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
822 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
823 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
904 * the order does not matter even for skl+. in intel_crtc_planes_update_noarm()
932 memcpy(ddb, old_crtc_state->wm.skl.plane_ddb, in skl_crtc_planes_update_arm()
933 sizeof(old_crtc_state->wm.skl.plane_ddb)); in skl_crtc_planes_update_arm()
934 memcpy(ddb_y, old_crtc_state->wm.skl in skl_crtc_planes_update_arm()
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H A Dintel_dpll_mgr.h274 struct skl_dpll_hw_state skl; member
H A Dintel_dpll_mgr.c1384 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_enable()
1406 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_enable()
1431 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_hw_state()
1469 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_get_hw_state()
1742 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_wrpll_get_freq()
1813 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_hdmi_pll_dividers()
1851 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_dp_set_dpll_hw_state()
1890 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_lcpll_get_freq()
1969 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_freq()
1990 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_dump_hw_state()
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H A Dintel_cursor.c633 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_cursor_wm()
635 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
H A Dskl_universal_plane.c571 * Display WA #0731: skl in skl_plane_can_async_flip()
572 * WaDisableRCWithAsyncFlip: skl in skl_plane_can_async_flip()
833 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
835 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_plane_wm()
837 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
838 const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_write_plane_wm()
840 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; in skl_write_plane_wm()
2447 /* Display WA #0870: skl, bxt */ in skl_plane_has_planar()
H A Dintel_display_debugfs.c668 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; in i915_ddb_info()
674 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; in i915_ddb_info()
H A Dintel_bw.c1344 &crtc_state->wm.skl.plane_ddb[plane_id], in skl_crtc_calc_dbuf_bw()
1349 &crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_crtc_calc_dbuf_bw()
H A Dintel_display.c6949 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6988 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6992 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
7003 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7004 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
7077 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7080 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
H A Dintel_display_types.h898 } skl; member
H A Dintel_dmc.c174 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27)
/linux/sound/soc/sof/intel/
H A DMakefile34 snd-sof-pci-intel-skl-y := pci-skl.o skl.o hda-loader-skl.o
44 obj-$(CONFIG_SND_SOC_SOF_INTEL_SKL) += snd-sof-pci-intel-skl.o
/linux/sound/soc/intel/avs/
H A DMakefile7 snd-soc-avs-y += skl.o apl.o cnl.o icl.o tgl.o mtl.o lnl.o ptl.o
H A Dskl.c178 AVS_SET_ENABLE_LOGS_OP(skl)
/linux/sound/soc/intel/common/
H A DMakefile4 soc-acpi-intel-skl-match.o soc-acpi-intel-kbl-match.o \
/linux/drivers/platform/x86/intel/int3472/
H A DKconfig31 The module will be named "intel-skl-int3472".
/linux/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c51 * WaCompressedResourceDisplayNewHashMode:skl,kbl in gen9_init_clock_gating()
52 * Display WA #0390: skl,kbl in gen9_init_clock_gating()
60 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ in gen9_init_clock_gating()
63 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ in gen9_init_clock_gating()
67 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl in gen9_init_clock_gating()
68 * Display WA #0859: skl,bxt,kbl,glk,cfl in gen9_init_clock_gating()
408 /* WaDisableDopClockGating:skl */ in skl_init_clock_gating()
412 /* WAC6entrylatency:skl */ in skl_init_clock_gating()
416 * WaFbcTurnOffFbcWatermark:skl in skl_init_clock_gating()
417 * Display WA #0562: skl in skl_init_clock_gating()
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