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/linux/arch/arm64/include/asm/
H A Dcmpxchg.h21 #define __XCHG_CASE(w, sfx, name, sz, mb, nop_lse, acq, acq_lse, rel, cl) \ argument
30 "1: ld" #acq "xr" #sfx "\t%" #w "0, %2\n" \
31 " st" #rel "xr" #sfx "\t%w1, %" #w "3, %2\n" \
35 " swp" #acq_lse #rel #sfx "\t%" #w "3, %" #w "0, %2\n" \
64 #define __XCHG_GEN(sfx) \ argument
66 __arch_xchg##sfx(unsigned long x, volatile void *ptr, int size) \
70 return __xchg_case##sfx##_8(x, ptr); \
72 return __xchg_case##sfx##_16(x, ptr); \
74 return __xchg_case##sfx##_32(x, ptr); \
76 return __xchg_case##sfx##_6
91 __xchg_wrapper(sfx,ptr,x) global() argument
146 __CMPXCHG_GEN(sfx) global() argument
175 __cmpxchg_wrapper(sfx,ptr,o,n) global() argument
211 __CMPWAIT_CASE(w,sfx,sz) global() argument
236 __CMPWAIT_GEN(sfx) global() argument
[all...]
H A Drwonce.h15 #define __LOAD_RCPC(sfx, regs...) \ argument
17 "ldar" #sfx "\t" #regs, \
19 "ldapr" #sfx "\t" #regs, \
H A Dpercpu.h66 #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
75 "1: ldxr" #sfx "\t%" #w "[tmp], %[ptr]\n" \
77 " stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \
87 #define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ argument
96 "1: ldxr" #sfx "\t%" #w "[ret], %[ptr]\n" \
98 " stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \
H A Datomic_ll_sc.h239 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \ argument
258 "1: ld" #acq "xr" #sfx "\t%" #w "[oldval], %[v]\n" \
261 " st" #rel "xr" #sfx "\t%w[tmp], %" #w "[new], %[v]\n" \
/linux/scripts/atomic/
H A Datomic-tbl.sh45 #find_template(tmpltype, pfx, name, sfx, order)
51 local sfx="$1"; shift
62 for base in "${pfx}${name}${sfx}${order}" "${pfx}${name}${sfx}" "${name}"; do
72 #find_fallback_template(pfx, name, sfx, order)
78 #find_kerneldoc_template(pfx, name, sfx, order)
185 #gen_template_kerneldoc(template, class, meta, pfx, name, sfx, order, atomic, int, args...)
193 local sfx="$1"; shift
198 local atomicname="${atomic}_${pfx}${name}${sfx}${order}"
227 #gen_kerneldoc(class, meta, pfx, name, sfx, orde
[all...]
H A Dgen-atomic-long.sh35 #gen_proto_order_variant(meta, pfx, name, sfx, order, arg...)
41 local sfx="$1"; shift
44 local atomicname="${pfx}${name}${sfx}${order}"
52 gen_kerneldoc "raw_" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "atomic_long" "long" "$@"
H A Dgen-atomic-instrumented.sh52 #gen_proto_order_variant(meta, pfx, name, sfx, order, atomic, int, arg...)
58 local sfx="$1"; shift
63 local atomicname="${atomic}_${pfx}${name}${sfx}${order}"
71 gen_kerneldoc "" "${meta}" "${pfx}" "${name}" "${sfx}" "${order}" "${atomic}" "${int}" "$@"
/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a73a4.c13 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
15 PORT_10(0, fn, pfx, sfx), \
16 PORT_10(10, fn, pfx##1, sfx), \
17 PORT_10(20, fn, pfx##2, sfx), \
18 PORT_1(30, fn, pfx##30, sfx), \
20 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
21 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
22 PORT_1(36, fn, pfx##36, sfx), PORT_
[all...]
H A Dpfc-r8a779a0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
22 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
24 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
25 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAG
[all...]
H A Dpfc-sh73a0.c18 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
19 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
20 PORT_10(100, fn, pfx##10, sfx), \
21 PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
22 PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
23 PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
[all...]
H A Dpfc-emev2.c11 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
12 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
13 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
14 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
15 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
16 PORT_1(151, fn, pfx##151, sfx), PORT_
244 __PIN_CFG(pn,pfx,sfx) global() argument
253 __PORT_DATA(pn,pfx,sfx) global() argument
[all...]
H A Dpfc-r8a77470.c13 #define CPU_ALL_GP(fn, sfx) \ argument
14 PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_U
[all...]
H A Dpfc-r8a7794.c17 #define CPU_ALL_GP(fn, sfx) \ argument
18 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_1(5, 7, fn, sfx), \
25 PORT_GP_1(5, 8, fn, sfx), \
26 PORT_GP_1(5, 9, fn, sfx), \
[all...]
H A Dpfc-r8a7779.c14 #define CPU_ALL_GP(fn, sfx) \ argument
15 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_1(2, 1, fn, sfx), \
19 PORT_GP_1(2, 2, fn, sfx), \
20 PORT_GP_1(2, 3, fn, sfx), \
21 PORT_GP_1(2, 4, fn, sfx), \
22 PORT_GP_1(2, 5, fn, sfx), \
23 PORT_GP_1(2, 6, fn, sfx), \
[all...]
H A Dpfc-r8a779h0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAG
[all...]
/linux/arch/riscv/include/asm/
H A Datomic.h198 #define _arch_atomic_fetch_add_unless(_prev, _rc, counter, _a, _u, sfx) \ argument
201 "0: lr." sfx " %[p], %[c]\n" \
204 " sc." sfx ".rl %[rc], %[rc], %[c]\n" \
237 #define _arch_atomic_inc_unless_negative(_prev, _rc, counter, sfx) \ argument
240 "0: lr." sfx " %[p], %[c]\n" \
243 " sc." sfx ".rl %[rc], %[rc], %[c]\n" \
263 #define _arch_atomic_dec_unless_positive(_prev, _rc, counter, sfx) \ argument
266 "0: lr." sfx " %[p], %[c]\n" \
269 " sc." sfx ".rl %[rc], %[rc], %[c]\n" \
289 #define _arch_atomic_dec_if_positive(_prev, _rc, counter, sfx) \ argument
[all...]
/linux/include/linux/
H A Dbtree-type.h2 #define __BTREE_TP(pfx, type, sfx) pfx ## type ## sfx argument
3 #define _BTREE_TP(pfx, type, sfx) __BTREE_TP(pfx, type, sfx) argument
/linux/tools/testing/selftests/net/netfilter/
H A Dnft_audit.sh57 [[ "$pfx $sfx" == "$tpfx $tsfx" ]] && {
64 tsfx="$sfx"
H A Dnft_meta.sh7 sfx=$(mktemp -u "XXXXXXXX")
8 ns0="ns0-$sfx"
/linux/scripts/atomic/fallbacks/
H A Ddec2 ${retstmt}raw_${atomic}_${pfx}sub${sfx}${order}(1, v);
H A Dinc2 ${retstmt}raw_${atomic}_${pfx}add${sfx}${order}(1, v);
H A Drelease3 ${retstmt}arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});
H A Dandnot2 ${retstmt}raw_${atomic}_${pfx}and${sfx}${order}(~i, v);
H A Dacquire2 ${ret} ret = arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});
H A Dfence4 ret = arch_${atomic}_${pfx}${name}${sfx}_relaxed(${args});

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