1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_7.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_7_ppt.h"
39 #include "smu_v13_0_7_pptable.h"
40 #include "smu_v13_0_7_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028
72
73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
74
75 #define PP_OD_FEATURE_GFXCLK_FMIN 0
76 #define PP_OD_FEATURE_GFXCLK_FMAX 1
77 #define PP_OD_FEATURE_UCLK_FMIN 2
78 #define PP_OD_FEATURE_UCLK_FMAX 3
79 #define PP_OD_FEATURE_GFX_VF_CURVE 4
80 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
81 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
82 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
83 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
84 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
85 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
86 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
87 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
88
89 #define LINK_SPEED_MAX 3
90
91 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
116 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
117 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
118 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
119 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
120 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
121 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
122 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
123 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
124 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
125 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
126 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
127 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
129 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
130 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
131 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
132 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
133 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
134 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
135 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
136 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
137 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
138 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
139 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
140 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
141 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
142 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
143 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
144 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
145 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
146 };
147
148 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
149 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
150 CLK_MAP(SCLK, PPCLK_GFXCLK),
151 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
152 CLK_MAP(FCLK, PPCLK_FCLK),
153 CLK_MAP(UCLK, PPCLK_UCLK),
154 CLK_MAP(MCLK, PPCLK_UCLK),
155 CLK_MAP(VCLK, PPCLK_VCLK_0),
156 CLK_MAP(VCLK1, PPCLK_VCLK_1),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
160 };
161
162 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
163 FEA_MAP(FW_DATA_READ),
164 FEA_MAP(DPM_GFXCLK),
165 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
166 FEA_MAP(DPM_UCLK),
167 FEA_MAP(DPM_FCLK),
168 FEA_MAP(DPM_SOCCLK),
169 FEA_MAP(DPM_MP0CLK),
170 FEA_MAP(DPM_LINK),
171 FEA_MAP(DPM_DCN),
172 FEA_MAP(VMEMP_SCALING),
173 FEA_MAP(VDDIO_MEM_SCALING),
174 FEA_MAP(DS_GFXCLK),
175 FEA_MAP(DS_SOCCLK),
176 FEA_MAP(DS_FCLK),
177 FEA_MAP(DS_LCLK),
178 FEA_MAP(DS_DCFCLK),
179 FEA_MAP(DS_UCLK),
180 FEA_MAP(GFX_ULV),
181 FEA_MAP(FW_DSTATE),
182 FEA_MAP(GFXOFF),
183 FEA_MAP(BACO),
184 FEA_MAP(MM_DPM),
185 FEA_MAP(SOC_MPCLK_DS),
186 FEA_MAP(BACO_MPCLK_DS),
187 FEA_MAP(THROTTLERS),
188 FEA_MAP(SMARTSHIFT),
189 FEA_MAP(GTHR),
190 FEA_MAP(ACDC),
191 FEA_MAP(VR0HOT),
192 FEA_MAP(FW_CTF),
193 FEA_MAP(FAN_CONTROL),
194 FEA_MAP(GFX_DCS),
195 FEA_MAP(GFX_READ_MARGIN),
196 FEA_MAP(LED_DISPLAY),
197 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
198 FEA_MAP(OUT_OF_BAND_MONITOR),
199 FEA_MAP(OPTIMIZED_VMIN),
200 FEA_MAP(GFX_IMU),
201 FEA_MAP(BOOT_TIME_CAL),
202 FEA_MAP(GFX_PCC_DFLL),
203 FEA_MAP(SOC_CG),
204 FEA_MAP(DF_CSTATE),
205 FEA_MAP(GFX_EDC),
206 FEA_MAP(BOOT_POWER_OPT),
207 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
208 FEA_MAP(DS_VCN),
209 FEA_MAP(BACO_CG),
210 FEA_MAP(MEM_TEMP_READ),
211 FEA_MAP(ATHUB_MMHUB_PG),
212 FEA_MAP(SOC_PCC),
213 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
214 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
215 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
216 };
217
218 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
219 TAB_MAP(PPTABLE),
220 TAB_MAP(WATERMARKS),
221 TAB_MAP(AVFS_PSM_DEBUG),
222 TAB_MAP(PMSTATUSLOG),
223 TAB_MAP(SMU_METRICS),
224 TAB_MAP(DRIVER_SMU_CONFIG),
225 TAB_MAP(ACTIVITY_MONITOR_COEFF),
226 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
227 TAB_MAP(OVERDRIVE),
228 TAB_MAP(WIFIBAND),
229 };
230
231 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
232 PWR_MAP(AC),
233 PWR_MAP(DC),
234 };
235
236 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
240 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
241 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
242 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
243 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
244 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
245 };
246
247 static const uint8_t smu_v13_0_7_throttler_map[] = {
248 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
249 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
250 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
251 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
254 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
255 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
257 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
259 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
260 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
261 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
264 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
265 };
266
267 static int
smu_v13_0_7_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)268 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
269 uint32_t *feature_mask, uint32_t num)
270 {
271 struct amdgpu_device *adev = smu->adev;
272
273 if (num > 2)
274 return -EINVAL;
275
276 memset(feature_mask, 0, sizeof(uint32_t) * num);
277
278 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
279
280 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
284 }
285
286 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
288
289 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
294 }
295
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
297
298 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
300
301 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
303
304 if (adev->pm.pp_feature & PP_ULV_MASK)
305 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
306
307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
309 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
315 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
319 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
324 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
326
327 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
329
330 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
331 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
333
334 return 0;
335 }
336
smu_v13_0_7_check_powerplay_table(struct smu_context * smu)337 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
338 {
339 struct smu_table_context *table_context = &smu->smu_table;
340 struct smu_13_0_7_powerplay_table *powerplay_table =
341 table_context->power_play_table;
342 struct smu_baco_context *smu_baco = &smu->smu_baco;
343 PPTable_t *smc_pptable = table_context->driver_pptable;
344 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
345 const OverDriveLimits_t * const overdrive_upperlimits =
346 &smc_pptable->SkuTable.OverDriveLimitsBasicMax;
347 const OverDriveLimits_t * const overdrive_lowerlimits =
348 &smc_pptable->SkuTable.OverDriveLimitsMin;
349
350 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
351 smu->dc_controlled_by_gpio = true;
352
353 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) {
354 smu_baco->platform_support = true;
355
356 if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
357 && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
358 smu_baco->maco_support = true;
359 }
360
361 if (!overdrive_lowerlimits->FeatureCtrlMask ||
362 !overdrive_upperlimits->FeatureCtrlMask)
363 smu->od_enabled = false;
364
365 table_context->thermal_controller_type =
366 powerplay_table->thermal_controller_type;
367
368 /*
369 * Instead of having its own buffer space and get overdrive_table copied,
370 * smu->od_settings just points to the actual overdrive_table
371 */
372 smu->od_settings = &powerplay_table->overdrive_table;
373
374 return 0;
375 }
376
smu_v13_0_7_store_powerplay_table(struct smu_context * smu)377 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
378 {
379 struct smu_table_context *table_context = &smu->smu_table;
380 struct smu_13_0_7_powerplay_table *powerplay_table =
381 table_context->power_play_table;
382 struct amdgpu_device *adev = smu->adev;
383
384 if (adev->pdev->device == 0x51)
385 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
386
387 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
388 sizeof(PPTable_t));
389
390 return 0;
391 }
392
smu_v13_0_7_check_fw_status(struct smu_context * smu)393 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
394 {
395 struct amdgpu_device *adev = smu->adev;
396 uint32_t mp1_fw_flags;
397
398 mp1_fw_flags = RREG32_PCIE(MP1_Public |
399 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
400
401 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
402 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
403 return 0;
404
405 return -EIO;
406 }
407
408 #ifndef atom_smc_dpm_info_table_13_0_7
409 struct atom_smc_dpm_info_table_13_0_7 {
410 struct atom_common_table_header table_header;
411 BoardTable_t BoardTable;
412 };
413 #endif
414
smu_v13_0_7_append_powerplay_table(struct smu_context * smu)415 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
416 {
417 struct smu_table_context *table_context = &smu->smu_table;
418
419 PPTable_t *smc_pptable = table_context->driver_pptable;
420
421 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
422
423 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
424
425 int index, ret;
426
427 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
428 smc_dpm_info);
429
430 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
431 (uint8_t **)&smc_dpm_table);
432 if (ret)
433 return ret;
434
435 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
436
437 return 0;
438 }
439
smu_v13_0_7_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)440 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
441 void **table,
442 uint32_t *size)
443 {
444 struct smu_table_context *smu_table = &smu->smu_table;
445 void *combo_pptable = smu_table->combo_pptable;
446 int ret = 0;
447
448 ret = smu_cmn_get_combo_pptable(smu);
449 if (ret)
450 return ret;
451
452 *table = combo_pptable;
453 *size = sizeof(struct smu_13_0_7_powerplay_table);
454
455 return 0;
456 }
457
smu_v13_0_7_setup_pptable(struct smu_context * smu)458 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
459 {
460 struct smu_table_context *smu_table = &smu->smu_table;
461 struct amdgpu_device *adev = smu->adev;
462 int ret = 0;
463
464 /*
465 * With SCPM enabled, the pptable used will be signed. It cannot
466 * be used directly by driver. To get the raw pptable, we need to
467 * rely on the combo pptable(and its revelant SMU message).
468 */
469 ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
470 &smu_table->power_play_table,
471 &smu_table->power_play_table_size);
472 if (ret)
473 return ret;
474
475 ret = smu_v13_0_7_store_powerplay_table(smu);
476 if (ret)
477 return ret;
478
479 /*
480 * With SCPM enabled, the operation below will be handled
481 * by PSP. Driver involvment is unnecessary and useless.
482 */
483 if (!adev->scpm_enabled) {
484 ret = smu_v13_0_7_append_powerplay_table(smu);
485 if (ret)
486 return ret;
487 }
488
489 ret = smu_v13_0_7_check_powerplay_table(smu);
490 if (ret)
491 return ret;
492
493 return ret;
494 }
495
smu_v13_0_7_tables_init(struct smu_context * smu)496 static int smu_v13_0_7_tables_init(struct smu_context *smu)
497 {
498 struct smu_table_context *smu_table = &smu->smu_table;
499 struct smu_table *tables = smu_table->tables;
500
501 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503
504 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
506 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
507 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
508 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
509 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
510 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
512 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
513 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
514 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
515 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
516 AMDGPU_GEM_DOMAIN_VRAM);
517 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
518 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
519 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
520 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
521 AMDGPU_GEM_DOMAIN_VRAM);
522
523 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
524 if (!smu_table->metrics_table)
525 goto err0_out;
526 smu_table->metrics_time = 0;
527
528 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
529 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
530 if (!smu_table->gpu_metrics_table)
531 goto err1_out;
532
533 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
534 if (!smu_table->watermarks_table)
535 goto err2_out;
536
537 return 0;
538
539 err2_out:
540 kfree(smu_table->gpu_metrics_table);
541 err1_out:
542 kfree(smu_table->metrics_table);
543 err0_out:
544 return -ENOMEM;
545 }
546
smu_v13_0_7_allocate_dpm_context(struct smu_context * smu)547 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
548 {
549 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
550
551 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
552 GFP_KERNEL);
553 if (!smu_dpm->dpm_context)
554 return -ENOMEM;
555
556 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
557
558 return 0;
559 }
560
smu_v13_0_7_init_smc_tables(struct smu_context * smu)561 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
562 {
563 int ret = 0;
564
565 ret = smu_v13_0_7_tables_init(smu);
566 if (ret)
567 return ret;
568
569 ret = smu_v13_0_7_allocate_dpm_context(smu);
570 if (ret)
571 return ret;
572
573 return smu_v13_0_init_smc_tables(smu);
574 }
575
smu_v13_0_7_set_default_dpm_table(struct smu_context * smu)576 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
577 {
578 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
579 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
580 SkuTable_t *skutable = &driver_ppt->SkuTable;
581 struct smu_13_0_dpm_table *dpm_table;
582 int ret = 0;
583
584 /* socclk dpm table setup */
585 dpm_table = &dpm_context->dpm_tables.soc_table;
586 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
587 ret = smu_v13_0_set_single_dpm_table(smu,
588 SMU_SOCCLK,
589 dpm_table);
590 if (ret)
591 return ret;
592 } else {
593 dpm_table->count = 1;
594 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
595 dpm_table->dpm_levels[0].enabled = true;
596 dpm_table->min = dpm_table->dpm_levels[0].value;
597 dpm_table->max = dpm_table->dpm_levels[0].value;
598 }
599
600 /* gfxclk dpm table setup */
601 dpm_table = &dpm_context->dpm_tables.gfx_table;
602 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
603 ret = smu_v13_0_set_single_dpm_table(smu,
604 SMU_GFXCLK,
605 dpm_table);
606 if (ret)
607 return ret;
608
609 if (skutable->DriverReportedClocks.GameClockAc &&
610 (dpm_table->dpm_levels[dpm_table->count - 1].value >
611 skutable->DriverReportedClocks.GameClockAc)) {
612 dpm_table->dpm_levels[dpm_table->count - 1].value =
613 skutable->DriverReportedClocks.GameClockAc;
614 dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
615 }
616 } else {
617 dpm_table->count = 1;
618 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
619 dpm_table->dpm_levels[0].enabled = true;
620 dpm_table->min = dpm_table->dpm_levels[0].value;
621 dpm_table->max = dpm_table->dpm_levels[0].value;
622 }
623
624 /* uclk dpm table setup */
625 dpm_table = &dpm_context->dpm_tables.uclk_table;
626 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
627 ret = smu_v13_0_set_single_dpm_table(smu,
628 SMU_UCLK,
629 dpm_table);
630 if (ret)
631 return ret;
632 } else {
633 dpm_table->count = 1;
634 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
635 dpm_table->dpm_levels[0].enabled = true;
636 dpm_table->min = dpm_table->dpm_levels[0].value;
637 dpm_table->max = dpm_table->dpm_levels[0].value;
638 }
639
640 /* fclk dpm table setup */
641 dpm_table = &dpm_context->dpm_tables.fclk_table;
642 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
643 ret = smu_v13_0_set_single_dpm_table(smu,
644 SMU_FCLK,
645 dpm_table);
646 if (ret)
647 return ret;
648 } else {
649 dpm_table->count = 1;
650 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
651 dpm_table->dpm_levels[0].enabled = true;
652 dpm_table->min = dpm_table->dpm_levels[0].value;
653 dpm_table->max = dpm_table->dpm_levels[0].value;
654 }
655
656 /* vclk dpm table setup */
657 dpm_table = &dpm_context->dpm_tables.vclk_table;
658 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
659 ret = smu_v13_0_set_single_dpm_table(smu,
660 SMU_VCLK,
661 dpm_table);
662 if (ret)
663 return ret;
664 } else {
665 dpm_table->count = 1;
666 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
667 dpm_table->dpm_levels[0].enabled = true;
668 dpm_table->min = dpm_table->dpm_levels[0].value;
669 dpm_table->max = dpm_table->dpm_levels[0].value;
670 }
671
672 /* dclk dpm table setup */
673 dpm_table = &dpm_context->dpm_tables.dclk_table;
674 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
675 ret = smu_v13_0_set_single_dpm_table(smu,
676 SMU_DCLK,
677 dpm_table);
678 if (ret)
679 return ret;
680 } else {
681 dpm_table->count = 1;
682 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
683 dpm_table->dpm_levels[0].enabled = true;
684 dpm_table->min = dpm_table->dpm_levels[0].value;
685 dpm_table->max = dpm_table->dpm_levels[0].value;
686 }
687
688 /* dcefclk dpm table setup */
689 dpm_table = &dpm_context->dpm_tables.dcef_table;
690 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
691 ret = smu_v13_0_set_single_dpm_table(smu,
692 SMU_DCEFCLK,
693 dpm_table);
694 if (ret)
695 return ret;
696 } else {
697 dpm_table->count = 1;
698 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
699 dpm_table->dpm_levels[0].enabled = true;
700 dpm_table->min = dpm_table->dpm_levels[0].value;
701 dpm_table->max = dpm_table->dpm_levels[0].value;
702 }
703
704 return 0;
705 }
706
smu_v13_0_7_is_dpm_running(struct smu_context * smu)707 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
708 {
709 int ret = 0;
710 uint64_t feature_enabled;
711
712 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
713 if (ret)
714 return false;
715
716 return !!(feature_enabled & SMC_DPM_FEATURE);
717 }
718
smu_v13_0_7_get_throttler_status(SmuMetrics_t * metrics)719 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
720 {
721 uint32_t throttler_status = 0;
722 int i;
723
724 for (i = 0; i < THROTTLER_COUNT; i++)
725 throttler_status |=
726 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
727
728 return throttler_status;
729 }
730
731 #define SMU_13_0_7_BUSY_THRESHOLD 15
smu_v13_0_7_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)732 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
733 MetricsMember_t member,
734 uint32_t *value)
735 {
736 struct smu_table_context *smu_table = &smu->smu_table;
737 SmuMetrics_t *metrics =
738 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
739 int ret = 0;
740
741 ret = smu_cmn_get_metrics_table(smu,
742 NULL,
743 false);
744 if (ret)
745 return ret;
746
747 switch (member) {
748 case METRICS_CURR_GFXCLK:
749 *value = metrics->CurrClock[PPCLK_GFXCLK];
750 break;
751 case METRICS_CURR_SOCCLK:
752 *value = metrics->CurrClock[PPCLK_SOCCLK];
753 break;
754 case METRICS_CURR_UCLK:
755 *value = metrics->CurrClock[PPCLK_UCLK];
756 break;
757 case METRICS_CURR_VCLK:
758 *value = metrics->CurrClock[PPCLK_VCLK_0];
759 break;
760 case METRICS_CURR_VCLK1:
761 *value = metrics->CurrClock[PPCLK_VCLK_1];
762 break;
763 case METRICS_CURR_DCLK:
764 *value = metrics->CurrClock[PPCLK_DCLK_0];
765 break;
766 case METRICS_CURR_DCLK1:
767 *value = metrics->CurrClock[PPCLK_DCLK_1];
768 break;
769 case METRICS_CURR_FCLK:
770 *value = metrics->CurrClock[PPCLK_FCLK];
771 break;
772 case METRICS_CURR_DCEFCLK:
773 *value = metrics->CurrClock[PPCLK_DCFCLK];
774 break;
775 case METRICS_AVERAGE_GFXCLK:
776 *value = metrics->AverageGfxclkFrequencyPreDs;
777 break;
778 case METRICS_AVERAGE_FCLK:
779 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
780 *value = metrics->AverageFclkFrequencyPostDs;
781 else
782 *value = metrics->AverageFclkFrequencyPreDs;
783 break;
784 case METRICS_AVERAGE_UCLK:
785 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
786 *value = metrics->AverageMemclkFrequencyPostDs;
787 else
788 *value = metrics->AverageMemclkFrequencyPreDs;
789 break;
790 case METRICS_AVERAGE_VCNACTIVITY:
791 *value = max(metrics->Vcn0ActivityPercentage,
792 metrics->Vcn1ActivityPercentage);
793 break;
794 case METRICS_AVERAGE_VCLK:
795 *value = metrics->AverageVclk0Frequency;
796 break;
797 case METRICS_AVERAGE_DCLK:
798 *value = metrics->AverageDclk0Frequency;
799 break;
800 case METRICS_AVERAGE_VCLK1:
801 *value = metrics->AverageVclk1Frequency;
802 break;
803 case METRICS_AVERAGE_DCLK1:
804 *value = metrics->AverageDclk1Frequency;
805 break;
806 case METRICS_AVERAGE_GFXACTIVITY:
807 *value = metrics->AverageGfxActivity;
808 break;
809 case METRICS_AVERAGE_MEMACTIVITY:
810 *value = metrics->AverageUclkActivity;
811 break;
812 case METRICS_AVERAGE_SOCKETPOWER:
813 *value = metrics->AverageSocketPower << 8;
814 break;
815 case METRICS_TEMPERATURE_EDGE:
816 *value = metrics->AvgTemperature[TEMP_EDGE] *
817 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
818 break;
819 case METRICS_TEMPERATURE_HOTSPOT:
820 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
821 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
822 break;
823 case METRICS_TEMPERATURE_MEM:
824 *value = metrics->AvgTemperature[TEMP_MEM] *
825 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
826 break;
827 case METRICS_TEMPERATURE_VRGFX:
828 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
829 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
830 break;
831 case METRICS_TEMPERATURE_VRSOC:
832 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
833 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
834 break;
835 case METRICS_THROTTLER_STATUS:
836 *value = smu_v13_0_7_get_throttler_status(metrics);
837 break;
838 case METRICS_CURR_FANSPEED:
839 *value = metrics->AvgFanRpm;
840 break;
841 case METRICS_CURR_FANPWM:
842 *value = metrics->AvgFanPwm;
843 break;
844 case METRICS_VOLTAGE_VDDGFX:
845 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
846 break;
847 case METRICS_PCIE_RATE:
848 *value = metrics->PcieRate;
849 break;
850 case METRICS_PCIE_WIDTH:
851 *value = metrics->PcieWidth;
852 break;
853 default:
854 *value = UINT_MAX;
855 break;
856 }
857
858 return ret;
859 }
860
smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)861 static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
862 enum smu_clk_type clk_type,
863 uint32_t *min,
864 uint32_t *max)
865 {
866 struct smu_13_0_dpm_context *dpm_context =
867 smu->smu_dpm.dpm_context;
868 struct smu_13_0_dpm_table *dpm_table;
869
870 switch (clk_type) {
871 case SMU_MCLK:
872 case SMU_UCLK:
873 /* uclk dpm table */
874 dpm_table = &dpm_context->dpm_tables.uclk_table;
875 break;
876 case SMU_GFXCLK:
877 case SMU_SCLK:
878 /* gfxclk dpm table */
879 dpm_table = &dpm_context->dpm_tables.gfx_table;
880 break;
881 case SMU_SOCCLK:
882 /* socclk dpm table */
883 dpm_table = &dpm_context->dpm_tables.soc_table;
884 break;
885 case SMU_FCLK:
886 /* fclk dpm table */
887 dpm_table = &dpm_context->dpm_tables.fclk_table;
888 break;
889 case SMU_VCLK:
890 case SMU_VCLK1:
891 /* vclk dpm table */
892 dpm_table = &dpm_context->dpm_tables.vclk_table;
893 break;
894 case SMU_DCLK:
895 case SMU_DCLK1:
896 /* dclk dpm table */
897 dpm_table = &dpm_context->dpm_tables.dclk_table;
898 break;
899 default:
900 dev_err(smu->adev->dev, "Unsupported clock type!\n");
901 return -EINVAL;
902 }
903
904 if (min)
905 *min = dpm_table->min;
906 if (max)
907 *max = dpm_table->max;
908
909 return 0;
910 }
911
smu_v13_0_7_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)912 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
913 enum amd_pp_sensors sensor,
914 void *data,
915 uint32_t *size)
916 {
917 struct smu_table_context *table_context = &smu->smu_table;
918 PPTable_t *smc_pptable = table_context->driver_pptable;
919 int ret = 0;
920
921 switch (sensor) {
922 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
923 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
924 *size = 4;
925 break;
926 case AMDGPU_PP_SENSOR_MEM_LOAD:
927 ret = smu_v13_0_7_get_smu_metrics_data(smu,
928 METRICS_AVERAGE_MEMACTIVITY,
929 (uint32_t *)data);
930 *size = 4;
931 break;
932 case AMDGPU_PP_SENSOR_GPU_LOAD:
933 ret = smu_v13_0_7_get_smu_metrics_data(smu,
934 METRICS_AVERAGE_GFXACTIVITY,
935 (uint32_t *)data);
936 *size = 4;
937 break;
938 case AMDGPU_PP_SENSOR_VCN_LOAD:
939 ret = smu_v13_0_7_get_smu_metrics_data(smu,
940 METRICS_AVERAGE_VCNACTIVITY,
941 (uint32_t *)data);
942 *size = 4;
943 break;
944 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
945 ret = smu_v13_0_7_get_smu_metrics_data(smu,
946 METRICS_AVERAGE_SOCKETPOWER,
947 (uint32_t *)data);
948 *size = 4;
949 break;
950 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
951 ret = smu_v13_0_7_get_smu_metrics_data(smu,
952 METRICS_TEMPERATURE_HOTSPOT,
953 (uint32_t *)data);
954 *size = 4;
955 break;
956 case AMDGPU_PP_SENSOR_EDGE_TEMP:
957 ret = smu_v13_0_7_get_smu_metrics_data(smu,
958 METRICS_TEMPERATURE_EDGE,
959 (uint32_t *)data);
960 *size = 4;
961 break;
962 case AMDGPU_PP_SENSOR_MEM_TEMP:
963 ret = smu_v13_0_7_get_smu_metrics_data(smu,
964 METRICS_TEMPERATURE_MEM,
965 (uint32_t *)data);
966 *size = 4;
967 break;
968 case AMDGPU_PP_SENSOR_GFX_MCLK:
969 ret = smu_v13_0_7_get_smu_metrics_data(smu,
970 METRICS_CURR_UCLK,
971 (uint32_t *)data);
972 *(uint32_t *)data *= 100;
973 *size = 4;
974 break;
975 case AMDGPU_PP_SENSOR_GFX_SCLK:
976 ret = smu_v13_0_7_get_smu_metrics_data(smu,
977 METRICS_AVERAGE_GFXCLK,
978 (uint32_t *)data);
979 *(uint32_t *)data *= 100;
980 *size = 4;
981 break;
982 case AMDGPU_PP_SENSOR_VDDGFX:
983 ret = smu_v13_0_7_get_smu_metrics_data(smu,
984 METRICS_VOLTAGE_VDDGFX,
985 (uint32_t *)data);
986 *size = 4;
987 break;
988 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
989 default:
990 ret = -EOPNOTSUPP;
991 break;
992 }
993
994 return ret;
995 }
996
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)997 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
998 enum smu_clk_type clk_type,
999 uint32_t *value)
1000 {
1001 MetricsMember_t member_type;
1002 int clk_id = 0;
1003
1004 clk_id = smu_cmn_to_asic_specific_index(smu,
1005 CMN2ASIC_MAPPING_CLK,
1006 clk_type);
1007 if (clk_id < 0)
1008 return -EINVAL;
1009
1010 switch (clk_id) {
1011 case PPCLK_GFXCLK:
1012 member_type = METRICS_AVERAGE_GFXCLK;
1013 break;
1014 case PPCLK_UCLK:
1015 member_type = METRICS_CURR_UCLK;
1016 break;
1017 case PPCLK_FCLK:
1018 member_type = METRICS_CURR_FCLK;
1019 break;
1020 case PPCLK_SOCCLK:
1021 member_type = METRICS_CURR_SOCCLK;
1022 break;
1023 case PPCLK_VCLK_0:
1024 member_type = METRICS_CURR_VCLK;
1025 break;
1026 case PPCLK_DCLK_0:
1027 member_type = METRICS_CURR_DCLK;
1028 break;
1029 case PPCLK_VCLK_1:
1030 member_type = METRICS_CURR_VCLK1;
1031 break;
1032 case PPCLK_DCLK_1:
1033 member_type = METRICS_CURR_DCLK1;
1034 break;
1035 case PPCLK_DCFCLK:
1036 member_type = METRICS_CURR_DCEFCLK;
1037 break;
1038 default:
1039 return -EINVAL;
1040 }
1041
1042 return smu_v13_0_7_get_smu_metrics_data(smu,
1043 member_type,
1044 value);
1045 }
1046
smu_v13_0_7_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1047 static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
1048 int od_feature_bit)
1049 {
1050 PPTable_t *pptable = smu->smu_table.driver_pptable;
1051 const OverDriveLimits_t * const overdrive_upperlimits =
1052 &pptable->SkuTable.OverDriveLimitsBasicMax;
1053
1054 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1055 }
1056
smu_v13_0_7_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1057 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
1058 int od_feature_bit,
1059 int32_t *min,
1060 int32_t *max)
1061 {
1062 PPTable_t *pptable = smu->smu_table.driver_pptable;
1063 const OverDriveLimits_t * const overdrive_upperlimits =
1064 &pptable->SkuTable.OverDriveLimitsBasicMax;
1065 const OverDriveLimits_t * const overdrive_lowerlimits =
1066 &pptable->SkuTable.OverDriveLimitsMin;
1067 int32_t od_min_setting, od_max_setting;
1068
1069 switch (od_feature_bit) {
1070 case PP_OD_FEATURE_GFXCLK_FMIN:
1071 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1072 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1073 break;
1074 case PP_OD_FEATURE_GFXCLK_FMAX:
1075 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1076 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1077 break;
1078 case PP_OD_FEATURE_UCLK_FMIN:
1079 od_min_setting = overdrive_lowerlimits->UclkFmin;
1080 od_max_setting = overdrive_upperlimits->UclkFmin;
1081 break;
1082 case PP_OD_FEATURE_UCLK_FMAX:
1083 od_min_setting = overdrive_lowerlimits->UclkFmax;
1084 od_max_setting = overdrive_upperlimits->UclkFmax;
1085 break;
1086 case PP_OD_FEATURE_GFX_VF_CURVE:
1087 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1088 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1089 break;
1090 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1091 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1092 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1093 break;
1094 case PP_OD_FEATURE_FAN_CURVE_PWM:
1095 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1096 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1097 break;
1098 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1099 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1100 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1101 break;
1102 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1103 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1104 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1105 break;
1106 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1107 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1108 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1109 break;
1110 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1111 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1112 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1113 break;
1114 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1115 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1116 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1117 break;
1118 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1119 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1120 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1121 break;
1122 default:
1123 od_min_setting = od_max_setting = INT_MAX;
1124 break;
1125 }
1126
1127 if (min)
1128 *min = od_min_setting;
1129 if (max)
1130 *max = od_max_setting;
1131 }
1132
smu_v13_0_7_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1133 static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
1134 OverDriveTableExternal_t *od_table)
1135 {
1136 struct amdgpu_device *adev = smu->adev;
1137
1138 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1139 od_table->OverDriveTable.GfxclkFmax);
1140 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1141 od_table->OverDriveTable.UclkFmax);
1142 }
1143
smu_v13_0_7_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1144 static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
1145 OverDriveTableExternal_t *od_table)
1146 {
1147 int ret = 0;
1148
1149 ret = smu_cmn_update_table(smu,
1150 SMU_TABLE_OVERDRIVE,
1151 0,
1152 (void *)od_table,
1153 false);
1154 if (ret)
1155 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1156
1157 return ret;
1158 }
1159
smu_v13_0_7_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1160 static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
1161 OverDriveTableExternal_t *od_table)
1162 {
1163 int ret = 0;
1164
1165 ret = smu_cmn_update_table(smu,
1166 SMU_TABLE_OVERDRIVE,
1167 0,
1168 (void *)od_table,
1169 true);
1170 if (ret)
1171 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1172
1173 return ret;
1174 }
1175
smu_v13_0_7_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1176 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
1177 enum smu_clk_type clk_type,
1178 char *buf)
1179 {
1180 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1181 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1182 OverDriveTableExternal_t *od_table =
1183 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1184 struct smu_13_0_dpm_table *single_dpm_table;
1185 struct smu_13_0_pcie_table *pcie_table;
1186 uint32_t gen_speed, lane_width;
1187 int i, curr_freq, size = 0;
1188 int32_t min_value, max_value;
1189 int ret = 0;
1190
1191 smu_cmn_get_sysfs_buf(&buf, &size);
1192
1193 if (amdgpu_ras_intr_triggered()) {
1194 size += sysfs_emit_at(buf, size, "unavailable\n");
1195 return size;
1196 }
1197
1198 switch (clk_type) {
1199 case SMU_SCLK:
1200 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1201 break;
1202 case SMU_MCLK:
1203 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1204 break;
1205 case SMU_SOCCLK:
1206 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1207 break;
1208 case SMU_FCLK:
1209 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1210 break;
1211 case SMU_VCLK:
1212 case SMU_VCLK1:
1213 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1214 break;
1215 case SMU_DCLK:
1216 case SMU_DCLK1:
1217 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1218 break;
1219 case SMU_DCEFCLK:
1220 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1221 break;
1222 default:
1223 break;
1224 }
1225
1226 switch (clk_type) {
1227 case SMU_SCLK:
1228 case SMU_MCLK:
1229 case SMU_SOCCLK:
1230 case SMU_FCLK:
1231 case SMU_VCLK:
1232 case SMU_VCLK1:
1233 case SMU_DCLK:
1234 case SMU_DCLK1:
1235 case SMU_DCEFCLK:
1236 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1237 if (ret) {
1238 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1239 return ret;
1240 }
1241
1242 if (single_dpm_table->is_fine_grained) {
1243 /*
1244 * For fine grained dpms, there are only two dpm levels:
1245 * - level 0 -> min clock freq
1246 * - level 1 -> max clock freq
1247 * And the current clock frequency can be any value between them.
1248 * So, if the current clock frequency is not at level 0 or level 1,
1249 * we will fake it as three dpm levels:
1250 * - level 0 -> min clock freq
1251 * - level 1 -> current actual clock freq
1252 * - level 2 -> max clock freq
1253 */
1254 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1255 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1256 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1257 single_dpm_table->dpm_levels[0].value);
1258 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1259 curr_freq);
1260 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1261 single_dpm_table->dpm_levels[1].value);
1262 } else {
1263 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1264 single_dpm_table->dpm_levels[0].value,
1265 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1266 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1267 single_dpm_table->dpm_levels[1].value,
1268 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1269 }
1270 } else {
1271 for (i = 0; i < single_dpm_table->count; i++)
1272 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1273 i, single_dpm_table->dpm_levels[i].value,
1274 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1275 }
1276 break;
1277 case SMU_PCIE:
1278 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1279 METRICS_PCIE_RATE,
1280 &gen_speed);
1281 if (ret)
1282 return ret;
1283
1284 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1285 METRICS_PCIE_WIDTH,
1286 &lane_width);
1287 if (ret)
1288 return ret;
1289
1290 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1291 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1292 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1293 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1294 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1295 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1296 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1297 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1298 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1299 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1300 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1301 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1302 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1303 pcie_table->clk_freq[i],
1304 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1305 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1306 "*" : "");
1307 break;
1308
1309 case SMU_OD_SCLK:
1310 if (!smu_v13_0_7_is_od_feature_supported(smu,
1311 PP_OD_FEATURE_GFXCLK_BIT))
1312 break;
1313
1314 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1315 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1316 od_table->OverDriveTable.GfxclkFmin,
1317 od_table->OverDriveTable.GfxclkFmax);
1318 break;
1319
1320 case SMU_OD_MCLK:
1321 if (!smu_v13_0_7_is_od_feature_supported(smu,
1322 PP_OD_FEATURE_UCLK_BIT))
1323 break;
1324
1325 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1326 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1327 od_table->OverDriveTable.UclkFmin,
1328 od_table->OverDriveTable.UclkFmax);
1329 break;
1330
1331 case SMU_OD_VDDGFX_OFFSET:
1332 if (!smu_v13_0_7_is_od_feature_supported(smu,
1333 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1334 break;
1335
1336 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1337 size += sysfs_emit_at(buf, size, "%dmV\n",
1338 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1339 break;
1340
1341 case SMU_OD_FAN_CURVE:
1342 if (!smu_v13_0_7_is_od_feature_supported(smu,
1343 PP_OD_FEATURE_FAN_CURVE_BIT))
1344 break;
1345
1346 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1347 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1348 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1349 i,
1350 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1351 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1352
1353 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1354 smu_v13_0_7_get_od_setting_limits(smu,
1355 PP_OD_FEATURE_FAN_CURVE_TEMP,
1356 &min_value,
1357 &max_value);
1358 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1359 min_value, max_value);
1360
1361 smu_v13_0_7_get_od_setting_limits(smu,
1362 PP_OD_FEATURE_FAN_CURVE_PWM,
1363 &min_value,
1364 &max_value);
1365 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1366 min_value, max_value);
1367
1368 break;
1369
1370 case SMU_OD_ACOUSTIC_LIMIT:
1371 if (!smu_v13_0_7_is_od_feature_supported(smu,
1372 PP_OD_FEATURE_FAN_CURVE_BIT))
1373 break;
1374
1375 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1376 size += sysfs_emit_at(buf, size, "%d\n",
1377 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1378
1379 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1380 smu_v13_0_7_get_od_setting_limits(smu,
1381 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1382 &min_value,
1383 &max_value);
1384 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1385 min_value, max_value);
1386 break;
1387
1388 case SMU_OD_ACOUSTIC_TARGET:
1389 if (!smu_v13_0_7_is_od_feature_supported(smu,
1390 PP_OD_FEATURE_FAN_CURVE_BIT))
1391 break;
1392
1393 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1394 size += sysfs_emit_at(buf, size, "%d\n",
1395 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1396
1397 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1398 smu_v13_0_7_get_od_setting_limits(smu,
1399 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1400 &min_value,
1401 &max_value);
1402 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1403 min_value, max_value);
1404 break;
1405
1406 case SMU_OD_FAN_TARGET_TEMPERATURE:
1407 if (!smu_v13_0_7_is_od_feature_supported(smu,
1408 PP_OD_FEATURE_FAN_CURVE_BIT))
1409 break;
1410
1411 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1412 size += sysfs_emit_at(buf, size, "%d\n",
1413 (int)od_table->OverDriveTable.FanTargetTemperature);
1414
1415 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1416 smu_v13_0_7_get_od_setting_limits(smu,
1417 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1418 &min_value,
1419 &max_value);
1420 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1421 min_value, max_value);
1422 break;
1423
1424 case SMU_OD_FAN_MINIMUM_PWM:
1425 if (!smu_v13_0_7_is_od_feature_supported(smu,
1426 PP_OD_FEATURE_FAN_CURVE_BIT))
1427 break;
1428
1429 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1430 size += sysfs_emit_at(buf, size, "%d\n",
1431 (int)od_table->OverDriveTable.FanMinimumPwm);
1432
1433 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1434 smu_v13_0_7_get_od_setting_limits(smu,
1435 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1436 &min_value,
1437 &max_value);
1438 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1439 min_value, max_value);
1440 break;
1441
1442 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1443 if (!smu_v13_0_7_is_od_feature_supported(smu,
1444 PP_OD_FEATURE_ZERO_FAN_BIT))
1445 break;
1446
1447 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1448 size += sysfs_emit_at(buf, size, "%d\n",
1449 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1450
1451 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1452 smu_v13_0_7_get_od_setting_limits(smu,
1453 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1454 &min_value,
1455 &max_value);
1456 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1457 min_value, max_value);
1458 break;
1459
1460 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1461 if (!smu_v13_0_7_is_od_feature_supported(smu,
1462 PP_OD_FEATURE_ZERO_FAN_BIT))
1463 break;
1464
1465 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1466 size += sysfs_emit_at(buf, size, "%d\n",
1467 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1468
1469 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1470 smu_v13_0_7_get_od_setting_limits(smu,
1471 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1472 &min_value,
1473 &max_value);
1474 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1475 min_value, max_value);
1476 break;
1477
1478 case SMU_OD_RANGE:
1479 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1480 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1481 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1482 break;
1483
1484 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1485
1486 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1487 smu_v13_0_7_get_od_setting_limits(smu,
1488 PP_OD_FEATURE_GFXCLK_FMIN,
1489 &min_value,
1490 NULL);
1491 smu_v13_0_7_get_od_setting_limits(smu,
1492 PP_OD_FEATURE_GFXCLK_FMAX,
1493 NULL,
1494 &max_value);
1495 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1496 min_value, max_value);
1497 }
1498
1499 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1500 smu_v13_0_7_get_od_setting_limits(smu,
1501 PP_OD_FEATURE_UCLK_FMIN,
1502 &min_value,
1503 NULL);
1504 smu_v13_0_7_get_od_setting_limits(smu,
1505 PP_OD_FEATURE_UCLK_FMAX,
1506 NULL,
1507 &max_value);
1508 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1509 min_value, max_value);
1510 }
1511
1512 if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1513 smu_v13_0_7_get_od_setting_limits(smu,
1514 PP_OD_FEATURE_GFX_VF_CURVE,
1515 &min_value,
1516 &max_value);
1517 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1518 min_value, max_value);
1519 }
1520 break;
1521
1522 default:
1523 break;
1524 }
1525
1526 return size;
1527 }
1528
smu_v13_0_7_od_restore_table_single(struct smu_context * smu,long input)1529 static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input)
1530 {
1531 struct smu_table_context *table_context = &smu->smu_table;
1532 OverDriveTableExternal_t *boot_overdrive_table =
1533 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1534 OverDriveTableExternal_t *od_table =
1535 (OverDriveTableExternal_t *)table_context->overdrive_table;
1536 struct amdgpu_device *adev = smu->adev;
1537 int i;
1538
1539 switch (input) {
1540 case PP_OD_EDIT_FAN_CURVE:
1541 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1542 od_table->OverDriveTable.FanLinearTempPoints[i] =
1543 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1544 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1545 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1546 }
1547 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1548 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1549 break;
1550 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1551 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1552 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1553 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1554 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1555 break;
1556 case PP_OD_EDIT_ACOUSTIC_TARGET:
1557 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1558 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1559 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1560 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1561 break;
1562 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1563 od_table->OverDriveTable.FanTargetTemperature =
1564 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1565 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1566 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1567 break;
1568 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1569 od_table->OverDriveTable.FanMinimumPwm =
1570 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1571 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1572 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1573 break;
1574 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1575 od_table->OverDriveTable.FanZeroRpmEnable =
1576 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1577 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1578 break;
1579 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1580 od_table->OverDriveTable.FanZeroRpmStopTemp =
1581 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1582 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1583 break;
1584 default:
1585 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1586 return -EINVAL;
1587 }
1588
1589 return 0;
1590 }
1591
smu_v13_0_7_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1592 static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
1593 enum PP_OD_DPM_TABLE_COMMAND type,
1594 long input[],
1595 uint32_t size)
1596 {
1597 struct smu_table_context *table_context = &smu->smu_table;
1598 OverDriveTableExternal_t *od_table =
1599 (OverDriveTableExternal_t *)table_context->overdrive_table;
1600 struct amdgpu_device *adev = smu->adev;
1601 uint32_t offset_of_voltageoffset;
1602 int32_t minimum, maximum;
1603 uint32_t feature_ctrlmask;
1604 int i, ret = 0;
1605
1606 switch (type) {
1607 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1608 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1609 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1610 return -ENOTSUPP;
1611 }
1612
1613 for (i = 0; i < size; i += 2) {
1614 if (i + 2 > size) {
1615 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1616 return -EINVAL;
1617 }
1618
1619 switch (input[i]) {
1620 case 0:
1621 smu_v13_0_7_get_od_setting_limits(smu,
1622 PP_OD_FEATURE_GFXCLK_FMIN,
1623 &minimum,
1624 &maximum);
1625 if (input[i + 1] < minimum ||
1626 input[i + 1] > maximum) {
1627 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1628 input[i + 1], minimum, maximum);
1629 return -EINVAL;
1630 }
1631
1632 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1633 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1634 break;
1635
1636 case 1:
1637 smu_v13_0_7_get_od_setting_limits(smu,
1638 PP_OD_FEATURE_GFXCLK_FMAX,
1639 &minimum,
1640 &maximum);
1641 if (input[i + 1] < minimum ||
1642 input[i + 1] > maximum) {
1643 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1644 input[i + 1], minimum, maximum);
1645 return -EINVAL;
1646 }
1647
1648 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1649 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1650 break;
1651
1652 default:
1653 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1654 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1655 return -EINVAL;
1656 }
1657 }
1658
1659 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1660 dev_err(adev->dev,
1661 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1662 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1663 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1664 return -EINVAL;
1665 }
1666 break;
1667
1668 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1669 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1670 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1671 return -ENOTSUPP;
1672 }
1673
1674 for (i = 0; i < size; i += 2) {
1675 if (i + 2 > size) {
1676 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1677 return -EINVAL;
1678 }
1679
1680 switch (input[i]) {
1681 case 0:
1682 smu_v13_0_7_get_od_setting_limits(smu,
1683 PP_OD_FEATURE_UCLK_FMIN,
1684 &minimum,
1685 &maximum);
1686 if (input[i + 1] < minimum ||
1687 input[i + 1] > maximum) {
1688 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1689 input[i + 1], minimum, maximum);
1690 return -EINVAL;
1691 }
1692
1693 od_table->OverDriveTable.UclkFmin = input[i + 1];
1694 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1695 break;
1696
1697 case 1:
1698 smu_v13_0_7_get_od_setting_limits(smu,
1699 PP_OD_FEATURE_UCLK_FMAX,
1700 &minimum,
1701 &maximum);
1702 if (input[i + 1] < minimum ||
1703 input[i + 1] > maximum) {
1704 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1705 input[i + 1], minimum, maximum);
1706 return -EINVAL;
1707 }
1708
1709 od_table->OverDriveTable.UclkFmax = input[i + 1];
1710 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1711 break;
1712
1713 default:
1714 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1715 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1716 return -EINVAL;
1717 }
1718 }
1719
1720 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1721 dev_err(adev->dev,
1722 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1723 (uint32_t)od_table->OverDriveTable.UclkFmin,
1724 (uint32_t)od_table->OverDriveTable.UclkFmax);
1725 return -EINVAL;
1726 }
1727 break;
1728
1729 case PP_OD_EDIT_VDDGFX_OFFSET:
1730 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1731 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1732 return -ENOTSUPP;
1733 }
1734
1735 smu_v13_0_7_get_od_setting_limits(smu,
1736 PP_OD_FEATURE_GFX_VF_CURVE,
1737 &minimum,
1738 &maximum);
1739 if (input[0] < minimum ||
1740 input[0] > maximum) {
1741 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1742 input[0], minimum, maximum);
1743 return -EINVAL;
1744 }
1745
1746 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1747 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1748 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1749 break;
1750
1751 case PP_OD_EDIT_FAN_CURVE:
1752 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1753 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1754 return -ENOTSUPP;
1755 }
1756
1757 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1758 input[0] < 0)
1759 return -EINVAL;
1760
1761 smu_v13_0_7_get_od_setting_limits(smu,
1762 PP_OD_FEATURE_FAN_CURVE_TEMP,
1763 &minimum,
1764 &maximum);
1765 if (input[1] < minimum ||
1766 input[1] > maximum) {
1767 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1768 input[1], minimum, maximum);
1769 return -EINVAL;
1770 }
1771
1772 smu_v13_0_7_get_od_setting_limits(smu,
1773 PP_OD_FEATURE_FAN_CURVE_PWM,
1774 &minimum,
1775 &maximum);
1776 if (input[2] < minimum ||
1777 input[2] > maximum) {
1778 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1779 input[2], minimum, maximum);
1780 return -EINVAL;
1781 }
1782
1783 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1784 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1785 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1786 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1787 break;
1788
1789 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1790 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1791 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1792 return -ENOTSUPP;
1793 }
1794
1795 smu_v13_0_7_get_od_setting_limits(smu,
1796 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1797 &minimum,
1798 &maximum);
1799 if (input[0] < minimum ||
1800 input[0] > maximum) {
1801 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1802 input[0], minimum, maximum);
1803 return -EINVAL;
1804 }
1805
1806 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1807 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1808 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1809 break;
1810
1811 case PP_OD_EDIT_ACOUSTIC_TARGET:
1812 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1813 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1814 return -ENOTSUPP;
1815 }
1816
1817 smu_v13_0_7_get_od_setting_limits(smu,
1818 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1819 &minimum,
1820 &maximum);
1821 if (input[0] < minimum ||
1822 input[0] > maximum) {
1823 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1824 input[0], minimum, maximum);
1825 return -EINVAL;
1826 }
1827
1828 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1829 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1830 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1831 break;
1832
1833 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1834 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1835 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1836 return -ENOTSUPP;
1837 }
1838
1839 smu_v13_0_7_get_od_setting_limits(smu,
1840 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1841 &minimum,
1842 &maximum);
1843 if (input[0] < minimum ||
1844 input[0] > maximum) {
1845 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1846 input[0], minimum, maximum);
1847 return -EINVAL;
1848 }
1849
1850 od_table->OverDriveTable.FanTargetTemperature = input[0];
1851 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1852 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1853 break;
1854
1855 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1856 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1857 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1858 return -ENOTSUPP;
1859 }
1860
1861 smu_v13_0_7_get_od_setting_limits(smu,
1862 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1863 &minimum,
1864 &maximum);
1865 if (input[0] < minimum ||
1866 input[0] > maximum) {
1867 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1868 input[0], minimum, maximum);
1869 return -EINVAL;
1870 }
1871
1872 od_table->OverDriveTable.FanMinimumPwm = input[0];
1873 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1874 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1875 break;
1876
1877 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1878 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1879 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1880 return -ENOTSUPP;
1881 }
1882
1883 smu_v13_0_7_get_od_setting_limits(smu,
1884 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1885 &minimum,
1886 &maximum);
1887 if (input[0] < minimum ||
1888 input[0] > maximum) {
1889 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1890 input[0], minimum, maximum);
1891 return -EINVAL;
1892 }
1893
1894 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1895 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1896 break;
1897
1898 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1899 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1900 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1901 return -ENOTSUPP;
1902 }
1903
1904 smu_v13_0_7_get_od_setting_limits(smu,
1905 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1906 &minimum,
1907 &maximum);
1908 if (input[0] < minimum ||
1909 input[0] > maximum) {
1910 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1911 input[0], minimum, maximum);
1912 return -EINVAL;
1913 }
1914
1915 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1916 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1917 break;
1918
1919 case PP_OD_RESTORE_DEFAULT_TABLE:
1920 if (size == 1) {
1921 ret = smu_v13_0_7_od_restore_table_single(smu, input[0]);
1922 if (ret)
1923 return ret;
1924 } else {
1925 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1926 memcpy(od_table,
1927 table_context->boot_overdrive_table,
1928 sizeof(OverDriveTableExternal_t));
1929 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1930 }
1931 fallthrough;
1932
1933 case PP_OD_COMMIT_DPM_TABLE:
1934 /*
1935 * The member below instructs PMFW the settings focused in
1936 * this single operation.
1937 * `uint32_t FeatureCtrlMask;`
1938 * It does not contain actual informations about user's custom
1939 * settings. Thus we do not cache it.
1940 */
1941 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1942 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1943 table_context->user_overdrive_table + offset_of_voltageoffset,
1944 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1945 smu_v13_0_7_dump_od_table(smu, od_table);
1946
1947 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
1948 if (ret) {
1949 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1950 return ret;
1951 }
1952
1953 od_table->OverDriveTable.FeatureCtrlMask = 0;
1954 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1955 (u8 *)od_table + offset_of_voltageoffset,
1956 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1957
1958 if (!memcmp(table_context->user_overdrive_table,
1959 table_context->boot_overdrive_table,
1960 sizeof(OverDriveTableExternal_t)))
1961 smu->user_dpm_profile.user_od = false;
1962 else
1963 smu->user_dpm_profile.user_od = true;
1964 }
1965 break;
1966
1967 default:
1968 return -ENOSYS;
1969 }
1970
1971 return ret;
1972 }
1973
smu_v13_0_7_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1974 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1975 enum smu_clk_type clk_type,
1976 uint32_t mask)
1977 {
1978 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1979 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1980 struct smu_13_0_dpm_table *single_dpm_table;
1981 uint32_t soft_min_level, soft_max_level;
1982 uint32_t min_freq, max_freq;
1983 int ret = 0;
1984
1985 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1986 soft_max_level = mask ? (fls(mask) - 1) : 0;
1987
1988 switch (clk_type) {
1989 case SMU_GFXCLK:
1990 case SMU_SCLK:
1991 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1992 break;
1993 case SMU_MCLK:
1994 case SMU_UCLK:
1995 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1996 break;
1997 case SMU_SOCCLK:
1998 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1999 break;
2000 case SMU_FCLK:
2001 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
2002 break;
2003 case SMU_VCLK:
2004 case SMU_VCLK1:
2005 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
2006 break;
2007 case SMU_DCLK:
2008 case SMU_DCLK1:
2009 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
2010 break;
2011 default:
2012 break;
2013 }
2014
2015 switch (clk_type) {
2016 case SMU_GFXCLK:
2017 case SMU_SCLK:
2018 case SMU_MCLK:
2019 case SMU_UCLK:
2020 case SMU_SOCCLK:
2021 case SMU_FCLK:
2022 case SMU_VCLK:
2023 case SMU_VCLK1:
2024 case SMU_DCLK:
2025 case SMU_DCLK1:
2026 if (single_dpm_table->is_fine_grained) {
2027 /* There is only 2 levels for fine grained DPM */
2028 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2029 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2030 } else {
2031 if ((soft_max_level >= single_dpm_table->count) ||
2032 (soft_min_level >= single_dpm_table->count))
2033 return -EINVAL;
2034 }
2035
2036 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2037 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2038
2039 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2040 clk_type,
2041 min_freq,
2042 max_freq,
2043 false);
2044 break;
2045 case SMU_DCEFCLK:
2046 case SMU_PCIE:
2047 default:
2048 break;
2049 }
2050
2051 return ret;
2052 }
2053
2054 static const struct smu_temperature_range smu13_thermal_policy[] = {
2055 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2056 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2057 };
2058
smu_v13_0_7_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2059 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
2060 struct smu_temperature_range *range)
2061 {
2062 struct smu_table_context *table_context = &smu->smu_table;
2063 struct smu_13_0_7_powerplay_table *powerplay_table =
2064 table_context->power_play_table;
2065 PPTable_t *pptable = smu->smu_table.driver_pptable;
2066
2067 if (!range)
2068 return -EINVAL;
2069
2070 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2071
2072 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2073 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2074 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2075 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2076 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2077 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2078 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2079 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2080 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2081 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2082 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2083 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2084 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2085 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2086
2087 return 0;
2088 }
2089
smu_v13_0_7_get_gpu_metrics(struct smu_context * smu,void ** table)2090 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
2091 void **table)
2092 {
2093 struct smu_table_context *smu_table = &smu->smu_table;
2094 struct gpu_metrics_v1_3 *gpu_metrics =
2095 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2096 SmuMetricsExternal_t metrics_ext;
2097 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2098 int ret = 0;
2099
2100 ret = smu_cmn_get_metrics_table(smu,
2101 &metrics_ext,
2102 true);
2103 if (ret)
2104 return ret;
2105
2106 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2107
2108 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2109 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2110 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2111 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2112 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2113 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2114 metrics->AvgTemperature[TEMP_VR_MEM1]);
2115
2116 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2117 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2118 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2119 metrics->Vcn1ActivityPercentage);
2120
2121 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2122 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2123
2124 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2125 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2126 else
2127 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2128
2129 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2130 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2131 else
2132 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2133
2134 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2135 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2136 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2137 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2138
2139 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
2140 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2141 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2142 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2143 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2144 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2145 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2146
2147 gpu_metrics->throttle_status =
2148 smu_v13_0_7_get_throttler_status(metrics);
2149 gpu_metrics->indep_throttle_status =
2150 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2151 smu_v13_0_7_throttler_map);
2152
2153 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2154
2155 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2156 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2157 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2158 else
2159 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2160
2161 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2162
2163 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2164 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2165 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2166
2167 *table = (void *)gpu_metrics;
2168
2169 return sizeof(struct gpu_metrics_v1_3);
2170 }
2171
smu_v13_0_7_set_supported_od_feature_mask(struct smu_context * smu)2172 static void smu_v13_0_7_set_supported_od_feature_mask(struct smu_context *smu)
2173 {
2174 struct amdgpu_device *adev = smu->adev;
2175
2176 if (smu_v13_0_7_is_od_feature_supported(smu,
2177 PP_OD_FEATURE_FAN_CURVE_BIT))
2178 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2179 OD_OPS_SUPPORT_FAN_CURVE_SET |
2180 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2181 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2182 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2183 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2184 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2185 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2186 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2187 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2188 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2189 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2190 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2191 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2192 }
2193
smu_v13_0_7_set_default_od_settings(struct smu_context * smu)2194 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)
2195 {
2196 OverDriveTableExternal_t *od_table =
2197 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2198 OverDriveTableExternal_t *boot_od_table =
2199 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2200 OverDriveTableExternal_t *user_od_table =
2201 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2202 OverDriveTableExternal_t user_od_table_bak;
2203 int ret = 0;
2204 int i;
2205
2206 ret = smu_v13_0_7_get_overdrive_table(smu, boot_od_table);
2207 if (ret)
2208 return ret;
2209
2210 smu_v13_0_7_dump_od_table(smu, boot_od_table);
2211
2212 memcpy(od_table,
2213 boot_od_table,
2214 sizeof(OverDriveTableExternal_t));
2215
2216 /*
2217 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2218 * but we have to preserve user defined values in "user_od_table".
2219 */
2220 if (!smu->adev->in_suspend) {
2221 memcpy(user_od_table,
2222 boot_od_table,
2223 sizeof(OverDriveTableExternal_t));
2224 smu->user_dpm_profile.user_od = false;
2225 } else if (smu->user_dpm_profile.user_od) {
2226 memcpy(&user_od_table_bak,
2227 user_od_table,
2228 sizeof(OverDriveTableExternal_t));
2229 memcpy(user_od_table,
2230 boot_od_table,
2231 sizeof(OverDriveTableExternal_t));
2232 user_od_table->OverDriveTable.GfxclkFmin =
2233 user_od_table_bak.OverDriveTable.GfxclkFmin;
2234 user_od_table->OverDriveTable.GfxclkFmax =
2235 user_od_table_bak.OverDriveTable.GfxclkFmax;
2236 user_od_table->OverDriveTable.UclkFmin =
2237 user_od_table_bak.OverDriveTable.UclkFmin;
2238 user_od_table->OverDriveTable.UclkFmax =
2239 user_od_table_bak.OverDriveTable.UclkFmax;
2240 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2241 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2242 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2243 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2244 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2245 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2246 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2247 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2248 }
2249 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2250 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2251 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2252 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2253 user_od_table->OverDriveTable.FanTargetTemperature =
2254 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2255 user_od_table->OverDriveTable.FanMinimumPwm =
2256 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2257 user_od_table->OverDriveTable.FanZeroRpmEnable =
2258 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2259 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2260 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2261 }
2262
2263 smu_v13_0_7_set_supported_od_feature_mask(smu);
2264
2265 return 0;
2266 }
2267
smu_v13_0_7_restore_user_od_settings(struct smu_context * smu)2268 static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu)
2269 {
2270 struct smu_table_context *table_context = &smu->smu_table;
2271 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2272 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2273 int res;
2274
2275 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2276 BIT(PP_OD_FEATURE_UCLK_BIT) |
2277 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2278 BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2279 res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table);
2280 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2281 if (res == 0)
2282 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2283
2284 return res;
2285 }
2286
smu_v13_0_7_populate_umd_state_clk(struct smu_context * smu)2287 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
2288 {
2289 struct smu_13_0_dpm_context *dpm_context =
2290 smu->smu_dpm.dpm_context;
2291 struct smu_13_0_dpm_table *gfx_table =
2292 &dpm_context->dpm_tables.gfx_table;
2293 struct smu_13_0_dpm_table *mem_table =
2294 &dpm_context->dpm_tables.uclk_table;
2295 struct smu_13_0_dpm_table *soc_table =
2296 &dpm_context->dpm_tables.soc_table;
2297 struct smu_13_0_dpm_table *vclk_table =
2298 &dpm_context->dpm_tables.vclk_table;
2299 struct smu_13_0_dpm_table *dclk_table =
2300 &dpm_context->dpm_tables.dclk_table;
2301 struct smu_13_0_dpm_table *fclk_table =
2302 &dpm_context->dpm_tables.fclk_table;
2303 struct smu_umd_pstate_table *pstate_table =
2304 &smu->pstate_table;
2305 struct smu_table_context *table_context = &smu->smu_table;
2306 PPTable_t *pptable = table_context->driver_pptable;
2307 DriverReportedClocks_t driver_clocks =
2308 pptable->SkuTable.DriverReportedClocks;
2309
2310 pstate_table->gfxclk_pstate.min = gfx_table->min;
2311 if (driver_clocks.GameClockAc &&
2312 (driver_clocks.GameClockAc < gfx_table->max))
2313 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2314 else
2315 pstate_table->gfxclk_pstate.peak = gfx_table->max;
2316
2317 pstate_table->uclk_pstate.min = mem_table->min;
2318 pstate_table->uclk_pstate.peak = mem_table->max;
2319
2320 pstate_table->socclk_pstate.min = soc_table->min;
2321 pstate_table->socclk_pstate.peak = soc_table->max;
2322
2323 pstate_table->vclk_pstate.min = vclk_table->min;
2324 pstate_table->vclk_pstate.peak = vclk_table->max;
2325
2326 pstate_table->dclk_pstate.min = dclk_table->min;
2327 pstate_table->dclk_pstate.peak = dclk_table->max;
2328
2329 pstate_table->fclk_pstate.min = fclk_table->min;
2330 pstate_table->fclk_pstate.peak = fclk_table->max;
2331
2332 if (driver_clocks.BaseClockAc &&
2333 driver_clocks.BaseClockAc < gfx_table->max)
2334 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2335 else
2336 pstate_table->gfxclk_pstate.standard = gfx_table->max;
2337 pstate_table->uclk_pstate.standard = mem_table->max;
2338 pstate_table->socclk_pstate.standard = soc_table->min;
2339 pstate_table->vclk_pstate.standard = vclk_table->min;
2340 pstate_table->dclk_pstate.standard = dclk_table->min;
2341 pstate_table->fclk_pstate.standard = fclk_table->min;
2342
2343 return 0;
2344 }
2345
smu_v13_0_7_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2346 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
2347 uint32_t *speed)
2348 {
2349 int ret;
2350
2351 if (!speed)
2352 return -EINVAL;
2353
2354 ret = smu_v13_0_7_get_smu_metrics_data(smu,
2355 METRICS_CURR_FANPWM,
2356 speed);
2357 if (ret) {
2358 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2359 return ret;
2360 }
2361
2362 /* Convert the PMFW output which is in percent to pwm(255) based */
2363 *speed = min(*speed * 255 / 100, (uint32_t)255);
2364
2365 return 0;
2366 }
2367
smu_v13_0_7_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2368 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
2369 uint32_t *speed)
2370 {
2371 if (!speed)
2372 return -EINVAL;
2373
2374 return smu_v13_0_7_get_smu_metrics_data(smu,
2375 METRICS_CURR_FANSPEED,
2376 speed);
2377 }
2378
smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context * smu)2379 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
2380 {
2381 struct smu_table_context *table_context = &smu->smu_table;
2382 PPTable_t *pptable = table_context->driver_pptable;
2383 SkuTable_t *skutable = &pptable->SkuTable;
2384
2385 /*
2386 * Skip the MGpuFanBoost setting for those ASICs
2387 * which do not support it
2388 */
2389 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2390 return 0;
2391
2392 return smu_cmn_send_smc_msg_with_param(smu,
2393 SMU_MSG_SetMGpuFanBoostLimitRpm,
2394 0,
2395 NULL);
2396 }
2397
smu_v13_0_7_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2398 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
2399 uint32_t *current_power_limit,
2400 uint32_t *default_power_limit,
2401 uint32_t *max_power_limit,
2402 uint32_t *min_power_limit)
2403 {
2404 struct smu_table_context *table_context = &smu->smu_table;
2405 struct smu_13_0_7_powerplay_table *powerplay_table =
2406 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
2407 PPTable_t *pptable = table_context->driver_pptable;
2408 SkuTable_t *skutable = &pptable->SkuTable;
2409 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2410 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2411
2412 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2413 power_limit = smu->adev->pm.ac_power ?
2414 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2415 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2416
2417 if (current_power_limit)
2418 *current_power_limit = power_limit;
2419 if (default_power_limit)
2420 *default_power_limit = power_limit;
2421
2422 if (powerplay_table) {
2423 if (smu->od_enabled &&
2424 (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT))) {
2425 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2426 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2427 } else if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2428 od_percent_upper = 0;
2429 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2430 }
2431 }
2432
2433 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2434 od_percent_upper, od_percent_lower, power_limit);
2435
2436 if (max_power_limit) {
2437 *max_power_limit = msg_limit * (100 + od_percent_upper);
2438 *max_power_limit /= 100;
2439 }
2440
2441 if (min_power_limit) {
2442 *min_power_limit = power_limit * (100 - od_percent_lower);
2443 *min_power_limit /= 100;
2444 }
2445
2446 return 0;
2447 }
2448
smu_v13_0_7_get_power_profile_mode(struct smu_context * smu,char * buf)2449 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
2450 {
2451 DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external;
2452 uint32_t i, j, size = 0;
2453 int16_t workload_type = 0;
2454 int result = 0;
2455
2456 if (!buf)
2457 return -EINVAL;
2458
2459 activity_monitor_external = kcalloc(PP_SMC_POWER_PROFILE_COUNT,
2460 sizeof(*activity_monitor_external),
2461 GFP_KERNEL);
2462 if (!activity_monitor_external)
2463 return -ENOMEM;
2464
2465 size += sysfs_emit_at(buf, size, " ");
2466 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
2467 size += sysfs_emit_at(buf, size, "%d %-14s%s", i, amdgpu_pp_profile_name[i],
2468 (i == smu->power_profile_mode) ? "* " : " ");
2469
2470 size += sysfs_emit_at(buf, size, "\n");
2471
2472 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
2473 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2474 workload_type = smu_cmn_to_asic_specific_index(smu,
2475 CMN2ASIC_MAPPING_WORKLOAD,
2476 i);
2477 if (workload_type == -ENOTSUPP)
2478 continue;
2479 else if (workload_type < 0) {
2480 result = -EINVAL;
2481 goto out;
2482 }
2483
2484 result = smu_cmn_update_table(smu,
2485 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
2486 (void *)(&activity_monitor_external[i]), false);
2487 if (result) {
2488 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2489 goto out;
2490 }
2491 }
2492
2493 #define PRINT_DPM_MONITOR(field) \
2494 do { \
2495 size += sysfs_emit_at(buf, size, "%-30s", #field); \
2496 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \
2497 size += sysfs_emit_at(buf, size, "%-18d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
2498 size += sysfs_emit_at(buf, size, "\n"); \
2499 } while (0)
2500
2501 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
2502 PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
2503 PRINT_DPM_MONITOR(Gfx_FPS);
2504 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
2505 PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
2506 PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
2507 PRINT_DPM_MONITOR(Gfx_BoosterFreq);
2508 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
2509 PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
2510 PRINT_DPM_MONITOR(Fclk_FPS);
2511 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
2512 PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
2513 PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
2514 PRINT_DPM_MONITOR(Fclk_BoosterFreq);
2515 #undef PRINT_DPM_MONITOR
2516
2517 result = size;
2518 out:
2519 kfree(activity_monitor_external);
2520 return result;
2521 }
2522
2523 #define SMU_13_0_7_CUSTOM_PARAMS_COUNT 8
2524 #define SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT 2
2525 #define SMU_13_0_7_CUSTOM_PARAMS_SIZE (SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_7_CUSTOM_PARAMS_COUNT * sizeof(long))
2526
smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2527 static int smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context *smu,
2528 long *input)
2529 {
2530
2531 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2532 DpmActivityMonitorCoeffInt_t *activity_monitor =
2533 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2534 int ret, idx;
2535
2536 ret = smu_cmn_update_table(smu,
2537 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2538 (void *)(&activity_monitor_external), false);
2539 if (ret) {
2540 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2541 return ret;
2542 }
2543
2544 idx = 0 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2545 if (input[idx]) {
2546 /* Gfxclk */
2547 activity_monitor->Gfx_ActiveHystLimit = input[idx + 1];
2548 activity_monitor->Gfx_IdleHystLimit = input[idx + 2];
2549 activity_monitor->Gfx_FPS = input[idx + 3];
2550 activity_monitor->Gfx_MinActiveFreqType = input[idx + 4];
2551 activity_monitor->Gfx_BoosterFreqType = input[idx + 5];
2552 activity_monitor->Gfx_MinActiveFreq = input[idx + 6];
2553 activity_monitor->Gfx_BoosterFreq = input[idx + 7];
2554 }
2555 idx = 1 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2556 if (input[idx]) {
2557 /* Fclk */
2558 activity_monitor->Fclk_ActiveHystLimit = input[idx + 1];
2559 activity_monitor->Fclk_IdleHystLimit = input[idx + 2];
2560 activity_monitor->Fclk_FPS = input[idx + 3];
2561 activity_monitor->Fclk_MinActiveFreqType = input[idx + 4];
2562 activity_monitor->Fclk_BoosterFreqType = input[idx + 5];
2563 activity_monitor->Fclk_MinActiveFreq = input[idx + 6];
2564 activity_monitor->Fclk_BoosterFreq = input[idx + 7];
2565 }
2566
2567 ret = smu_cmn_update_table(smu,
2568 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2569 (void *)(&activity_monitor_external), true);
2570 if (ret) {
2571 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2572 return ret;
2573 }
2574
2575 return ret;
2576 }
2577
smu_v13_0_7_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2578 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu,
2579 u32 workload_mask,
2580 long *custom_params,
2581 u32 custom_params_max_idx)
2582 {
2583 u32 backend_workload_mask = 0;
2584 int ret, idx = -1, i;
2585
2586 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2587 &backend_workload_mask);
2588
2589 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2590 if (!smu->custom_profile_params) {
2591 smu->custom_profile_params =
2592 kzalloc(SMU_13_0_7_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2593 if (!smu->custom_profile_params)
2594 return -ENOMEM;
2595 }
2596 if (custom_params && custom_params_max_idx) {
2597 if (custom_params_max_idx != SMU_13_0_7_CUSTOM_PARAMS_COUNT)
2598 return -EINVAL;
2599 if (custom_params[0] >= SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT)
2600 return -EINVAL;
2601 idx = custom_params[0] * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2602 smu->custom_profile_params[idx] = 1;
2603 for (i = 1; i < custom_params_max_idx; i++)
2604 smu->custom_profile_params[idx + i] = custom_params[i];
2605 }
2606 ret = smu_v13_0_7_set_power_profile_mode_coeff(smu,
2607 smu->custom_profile_params);
2608 if (ret) {
2609 if (idx != -1)
2610 smu->custom_profile_params[idx] = 0;
2611 return ret;
2612 }
2613 } else if (smu->custom_profile_params) {
2614 memset(smu->custom_profile_params, 0, SMU_13_0_7_CUSTOM_PARAMS_SIZE);
2615 }
2616
2617 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2618 backend_workload_mask, NULL);
2619
2620 if (ret) {
2621 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2622 workload_mask);
2623 if (idx != -1)
2624 smu->custom_profile_params[idx] = 0;
2625 return ret;
2626 }
2627
2628 return ret;
2629 }
2630
smu_v13_0_7_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2631 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
2632 enum pp_mp1_state mp1_state)
2633 {
2634 int ret;
2635
2636 switch (mp1_state) {
2637 case PP_MP1_STATE_UNLOAD:
2638 ret = smu_cmn_set_mp1_state(smu, mp1_state);
2639 break;
2640 default:
2641 /* Ignore others */
2642 ret = 0;
2643 }
2644
2645 return ret;
2646 }
2647
smu_v13_0_7_is_mode1_reset_supported(struct smu_context * smu)2648 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
2649 {
2650 struct amdgpu_device *adev = smu->adev;
2651
2652 /* SRIOV does not support SMU mode1 reset */
2653 if (amdgpu_sriov_vf(adev))
2654 return false;
2655
2656 return true;
2657 }
2658
smu_v13_0_7_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2659 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
2660 enum pp_df_cstate state)
2661 {
2662 return smu_cmn_send_smc_msg_with_param(smu,
2663 SMU_MSG_DFCstateControl,
2664 state,
2665 NULL);
2666 }
2667
smu_v13_0_7_wbrf_support_check(struct smu_context * smu)2668 static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
2669 {
2670 return smu->smc_fw_version > 0x00524600;
2671 }
2672
smu_v13_0_7_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2673 static int smu_v13_0_7_set_power_limit(struct smu_context *smu,
2674 enum smu_ppt_limit_type limit_type,
2675 uint32_t limit)
2676 {
2677 PPTable_t *pptable = smu->smu_table.driver_pptable;
2678 SkuTable_t *skutable = &pptable->SkuTable;
2679 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2680 struct smu_table_context *table_context = &smu->smu_table;
2681 OverDriveTableExternal_t *od_table =
2682 (OverDriveTableExternal_t *)table_context->overdrive_table;
2683 int ret = 0;
2684
2685 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2686 return -EINVAL;
2687
2688 if (limit <= msg_limit) {
2689 if (smu->current_power_limit > msg_limit) {
2690 od_table->OverDriveTable.Ppt = 0;
2691 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2692
2693 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2694 if (ret) {
2695 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2696 return ret;
2697 }
2698 }
2699 return smu_v13_0_set_power_limit(smu, limit_type, limit);
2700 } else if (smu->od_enabled) {
2701 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
2702 if (ret)
2703 return ret;
2704
2705 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2706 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2707
2708 ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2709 if (ret) {
2710 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2711 return ret;
2712 }
2713
2714 smu->current_power_limit = limit;
2715 } else {
2716 return -EINVAL;
2717 }
2718
2719 return 0;
2720 }
2721
smu_v13_0_7_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2722 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
2723 uint8_t pcie_gen_cap,
2724 uint8_t pcie_width_cap)
2725 {
2726 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2727 struct smu_13_0_pcie_table *pcie_table =
2728 &dpm_context->dpm_tables.pcie_table;
2729 int num_of_levels;
2730 int link_level;
2731 uint32_t smu_pcie_arg;
2732 struct smu_table_context *table_context = &smu->smu_table;
2733 PPTable_t *pptable = table_context->driver_pptable;
2734 SkuTable_t *skutable = &pptable->SkuTable;
2735 int ret = 0;
2736 int i;
2737
2738 pcie_table->num_of_link_levels = 0;
2739 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
2740 if (!skutable->PcieGenSpeed[link_level] &&
2741 !skutable->PcieLaneCount[link_level] &&
2742 !skutable->LclkFreq[link_level])
2743 continue;
2744
2745 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
2746 skutable->PcieGenSpeed[link_level];
2747 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
2748 skutable->PcieLaneCount[link_level];
2749 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
2750 skutable->LclkFreq[link_level];
2751 pcie_table->num_of_link_levels++;
2752 }
2753
2754 num_of_levels = pcie_table->num_of_link_levels;
2755 if (!num_of_levels)
2756 return 0;
2757
2758 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2759 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2760 pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2761
2762 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2763 pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2764
2765 /* Force all levels to use the same settings */
2766 for (i = 0; i < num_of_levels; i++) {
2767 pcie_table->pcie_gen[i] = pcie_gen_cap;
2768 pcie_table->pcie_lane[i] = pcie_width_cap;
2769 smu_pcie_arg = i << 16;
2770 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2771 smu_pcie_arg |= pcie_table->pcie_lane[i];
2772
2773 ret = smu_cmn_send_smc_msg_with_param(smu,
2774 SMU_MSG_OverridePcieParameters,
2775 smu_pcie_arg,
2776 NULL);
2777 if (ret)
2778 break;
2779 }
2780 } else {
2781 for (i = 0; i < num_of_levels; i++) {
2782 if (pcie_table->pcie_gen[i] > pcie_gen_cap ||
2783 pcie_table->pcie_lane[i] > pcie_width_cap) {
2784 pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ?
2785 pcie_gen_cap : pcie_table->pcie_gen[i];
2786 pcie_table->pcie_lane[i] = pcie_table->pcie_lane[i] > pcie_width_cap ?
2787 pcie_width_cap : pcie_table->pcie_lane[i];
2788 smu_pcie_arg = i << 16;
2789 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2790 smu_pcie_arg |= pcie_table->pcie_lane[i];
2791
2792 ret = smu_cmn_send_smc_msg_with_param(smu,
2793 SMU_MSG_OverridePcieParameters,
2794 smu_pcie_arg,
2795 NULL);
2796 if (ret)
2797 break;
2798 }
2799 }
2800 }
2801
2802 return ret;
2803 }
2804
2805 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
2806 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
2807 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
2808 .is_dpm_running = smu_v13_0_7_is_dpm_running,
2809 .init_microcode = smu_v13_0_init_microcode,
2810 .load_microcode = smu_v13_0_load_microcode,
2811 .fini_microcode = smu_v13_0_fini_microcode,
2812 .init_smc_tables = smu_v13_0_7_init_smc_tables,
2813 .fini_smc_tables = smu_v13_0_fini_smc_tables,
2814 .init_power = smu_v13_0_init_power,
2815 .fini_power = smu_v13_0_fini_power,
2816 .check_fw_status = smu_v13_0_7_check_fw_status,
2817 .setup_pptable = smu_v13_0_7_setup_pptable,
2818 .check_fw_version = smu_v13_0_check_fw_version,
2819 .write_pptable = smu_cmn_write_pptable,
2820 .set_driver_table_location = smu_v13_0_set_driver_table_location,
2821 .system_features_control = smu_v13_0_system_features_control,
2822 .set_allowed_mask = smu_v13_0_set_allowed_mask,
2823 .get_enabled_mask = smu_cmn_get_enabled_mask,
2824 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
2825 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
2826 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
2827 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
2828 .get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq,
2829 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2830 .read_sensor = smu_v13_0_7_read_sensor,
2831 .feature_is_enabled = smu_cmn_feature_is_enabled,
2832 .print_clk_levels = smu_v13_0_7_print_clk_levels,
2833 .force_clk_levels = smu_v13_0_7_force_clk_levels,
2834 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
2835 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
2836 .register_irq_handler = smu_v13_0_register_irq_handler,
2837 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2838 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2839 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2840 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
2841 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
2842 .set_default_od_settings = smu_v13_0_7_set_default_od_settings,
2843 .restore_user_od_settings = smu_v13_0_7_restore_user_od_settings,
2844 .od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table,
2845 .set_performance_level = smu_v13_0_set_performance_level,
2846 .gfx_off_control = smu_v13_0_gfx_off_control,
2847 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
2848 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
2849 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
2850 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
2851 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
2852 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
2853 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
2854 .get_power_limit = smu_v13_0_7_get_power_limit,
2855 .set_power_limit = smu_v13_0_7_set_power_limit,
2856 .set_power_source = smu_v13_0_set_power_source,
2857 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
2858 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
2859 .set_tool_table_location = smu_v13_0_set_tool_table_location,
2860 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2861 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2862 .get_bamaco_support = smu_v13_0_get_bamaco_support,
2863 .baco_enter = smu_v13_0_baco_enter,
2864 .baco_exit = smu_v13_0_baco_exit,
2865 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
2866 .mode1_reset = smu_v13_0_mode1_reset,
2867 .set_mp1_state = smu_v13_0_7_set_mp1_state,
2868 .set_df_cstate = smu_v13_0_7_set_df_cstate,
2869 .gpo_control = smu_v13_0_gpo_control,
2870 .is_asic_wbrf_supported = smu_v13_0_7_wbrf_support_check,
2871 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
2872 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
2873 .interrupt_work = smu_v13_0_interrupt_work,
2874 };
2875
smu_v13_0_7_set_ppt_funcs(struct smu_context * smu)2876 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
2877 {
2878 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
2879 smu->message_map = smu_v13_0_7_message_map;
2880 smu->clock_map = smu_v13_0_7_clk_map;
2881 smu->feature_map = smu_v13_0_7_feature_mask_map;
2882 smu->table_map = smu_v13_0_7_table_map;
2883 smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
2884 smu->workload_map = smu_v13_0_7_workload_map;
2885 smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION;
2886 smu_v13_0_set_smu_mailbox_registers(smu);
2887 }
2888