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Searched refs:scl_data (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp_dscl.c282 const struct scaler_data *scl_data, in dpp401_dscl_set_scl_filter() argument
290 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; in dpp401_dscl_set_scl_filter()
291 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp401_dscl_set_scl_filter()
299 filter_h = scl_data->dscl_prog_data.filter_h; in dpp401_dscl_set_scl_filter()
300 filter_v = scl_data->dscl_prog_data.filter_v; in dpp401_dscl_set_scl_filter()
302 filter_h_c = scl_data->dscl_prog_data.filter_h_c; in dpp401_dscl_set_scl_filter()
303 filter_v_c = scl_data->dscl_prog_data.filter_v_c; in dpp401_dscl_set_scl_filter()
307 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp401_dscl_set_scl_filter()
309 scl_data in dpp401_dscl_set_scl_filter()
476 dpp401_dscl_find_lb_memory_config(struct dcn401_dpp * dpp,const struct scaler_data * scl_data) dpp401_dscl_find_lb_memory_config() argument
668 dpp401_dscl_program_easf_v(struct dpp * dpp_base,const struct scaler_data * scl_data) dpp401_dscl_program_easf_v() argument
783 dpp401_dscl_program_easf_h(struct dpp * dpp_base,const struct scaler_data * scl_data) dpp401_dscl_program_easf_h() argument
888 dpp401_dscl_program_easf(struct dpp * dpp_base,const struct scaler_data * scl_data) dpp401_dscl_program_easf() argument
917 dpp401_dscl_disable_easf(struct dpp * dpp_base,const struct scaler_data * scl_data) dpp401_dscl_disable_easf() argument
961 dpp401_dscl_program_isharp(struct dpp * dpp_base,const struct scaler_data * scl_data,bool program_isharp_1dlut,bool * bs_coeffs_updated) dpp401_dscl_program_isharp() argument
1063 dpp401_dscl_set_scaler_manual_scale(struct dpp * dpp_base,const struct scaler_data * scl_data) dpp401_dscl_set_scaler_manual_scale() argument
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H A Ddcn401_dpp.c284 const struct scaler_data *scl_data, in dscl401_calc_lb_num_partitions() argument
292 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl401_calc_lb_num_partitions()
293 scl_data->viewport.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
294 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl401_calc_lb_num_partitions()
295 scl_data->viewport_c.width : scl_data->recout.width; in dscl401_calc_lb_num_partitions()
316 if (scl_data in dscl401_calc_lb_num_partitions()
359 dscl401_spl_calc_lb_num_partitions(bool alpha_en,const struct spl_scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c) dscl401_spl_calc_lb_num_partitions() argument
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/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl.c416 spl_scratch->scl_data.recout = shift_rec( in spl_calculate_recout()
419 spl_scratch->scl_data.recout.height -= in spl_calculate_recout()
421 spl_scratch->scl_data.recout.height -= in spl_calculate_recout()
425 memset(&spl_scratch->scl_data.recout, 0, in spl_calculate_recout()
445 spl_scratch->scl_data.ratios.horz = spl_fixpt_from_fraction( in spl_calculate_scaling_ratios()
448 spl_scratch->scl_data.ratios.vert = spl_fixpt_from_fraction( in spl_calculate_scaling_ratios()
453 spl_scratch->scl_data.ratios.horz.value *= 2; in spl_calculate_scaling_ratios()
455 spl_scratch->scl_data.ratios.vert.value *= 2; in spl_calculate_scaling_ratios()
457 spl_scratch->scl_data.ratios.vert.value = spl_div64_s64( in spl_calculate_scaling_ratios()
458 spl_scratch->scl_data in spl_calculate_scaling_ratios()
1178 spl_set_manual_ratio_init_data(struct dscl_prog_data * dscl_prog_data,const struct spl_scaler_data * scl_data) spl_set_manual_ratio_init_data() argument
1215 spl_set_taps_data(struct dscl_prog_data * dscl_prog_data,const struct spl_scaler_data * scl_data) spl_set_taps_data() argument
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H A Ddc_spl_types.h169 // MPC_SIZE - set based on scl_data h_active and v_active
174 // SCL_MODE - set based on scl_data.ratios and always_scale
184 // SCL_BLACK_COLOR - set based on scl_data.format
189 // RATIO - set based on scl_data.ratios
197 // INIT - set based on scl_data.init
219 // FILTER - calculated based on scl_data ratios and taps
257 struct spl_rect recout; // RECOUT - set based on scl_data.recout
263 struct spl_taps taps; // TAPS - set based on scl_data.taps
415 // Pack all SPL outputs in scl_data
416 struct spl_scaler_data scl_data; member
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
H A Ddcn32_dpp.c35 const struct scaler_data *scl_data, in dscl32_calc_lb_num_partitions() argument
43 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl32_calc_lb_num_partitions()
44 scl_data->viewport.width : scl_data->recout.width; in dscl32_calc_lb_num_partitions()
45 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl32_calc_lb_num_partitions()
46 scl_data->viewport_c.width : scl_data->recout.width; in dscl32_calc_lb_num_partitions()
67 if (scl_data in dscl32_calc_lb_num_partitions()
168 dscl32_spl_calc_lb_num_partitions(bool alpha_en,const struct spl_scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c) dscl32_spl_calc_lb_num_partitions() argument
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H A Ddcn32_dpp.h40 const struct spl_scaler_data *scl_data,
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c192 struct scaler_data *scl_data, in dpp201_get_optimal_number_of_taps() argument
196 if (scl_data->viewport.width != scl_data->h_active && in dpp201_get_optimal_number_of_taps()
197 scl_data->viewport.height != scl_data->v_active && in dpp201_get_optimal_number_of_taps()
199 scl_data->format == PIXEL_FORMAT_FP16) in dpp201_get_optimal_number_of_taps()
202 if (scl_data->viewport.width > scl_data->h_active && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
208 if (scl_data in dpp201_get_optimal_number_of_taps()
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H A Ddcn201_dpp.h72 struct scaler_data scl_data; member
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c280 const struct scaler_data *scl_data, in dpp1_dscl_set_scl_filter() argument
287 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; in dpp1_dscl_set_scl_filter()
288 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp1_dscl_set_scl_filter()
295 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
296 && scl_data->taps.h_taps_c < 3 in dpp1_dscl_set_scl_filter()
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
298 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
299 && scl_data->taps.v_taps_c < 3 in dpp1_dscl_set_scl_filter()
300 && (scl_data in dpp1_dscl_set_scl_filter()
392 dpp1_dscl_calc_lb_num_partitions(const struct scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c) dpp1_dscl_calc_lb_num_partitions() argument
460 dpp1_dscl_find_lb_memory_config(struct dcn10_dpp * dpp,const struct scaler_data * scl_data) dpp1_dscl_find_lb_memory_config() argument
614 dpp1_dscl_set_scaler_manual_scale(struct dpp * dpp_base,const struct scaler_data * scl_data) dpp1_dscl_set_scaler_manual_scale() argument
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H A Ddcn10_dpp.c126 struct scaler_data *scl_data, in dpp1_get_optimal_number_of_taps() argument
130 if (scl_data->format == PIXEL_FORMAT_FP16 && in dpp1_get_optimal_number_of_taps()
132 scl_data->ratios.horz.value != dc_fixpt_one.value && in dpp1_get_optimal_number_of_taps()
133 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp1_get_optimal_number_of_taps()
136 if (scl_data->viewport.width > scl_data->h_active && in dpp1_get_optimal_number_of_taps()
138 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp1_get_optimal_number_of_taps()
144 if (scl_data->ratios.horz.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
145 scl_data->ratios.horz.value--; in dpp1_get_optimal_number_of_taps()
146 if (scl_data in dpp1_get_optimal_number_of_taps()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp.c261 const struct scaler_data *scl_data, in dscl2_calc_lb_num_partitions() argument
269 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
270 scl_data->viewport.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
271 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
272 scl_data->viewport_c.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
306 if (scl_data in dscl2_calc_lb_num_partitions()
438 dscl2_spl_calc_lb_num_partitions(bool alpha_en,const struct spl_scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c) dscl2_spl_calc_lb_num_partitions() argument
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c420 struct scaler_data *scl_data, in dpp3_get_optimal_number_of_taps() argument
434 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) in dpp3_get_optimal_number_of_taps()
435 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
437 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
439 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
441 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) in dpp3_get_optimal_number_of_taps()
442 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
444 scl_data in dpp3_get_optimal_number_of_taps()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce60/
H A Ddce60_hwseq.c151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors()
158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors()
202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
312 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce60_program_front_end_for_pipe()
371 pipe_ctx->plane_res.scl_data.viewport.width, in dce60_program_front_end_for_pipe()
372 pipe_ctx->plane_res.scl_data.viewport.height, in dce60_program_front_end_for_pipe()
373 pipe_ctx->plane_res.scl_data.viewport.x, in dce60_program_front_end_for_pipe()
374 pipe_ctx->plane_res.scl_data in dce60_program_front_end_for_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_spl_translate.c97 // Make format field from spl_in point to plane_res scl_data format in translate_SPL_in_params_from_pipe_ctx()
98 populate_splformat_from_format(&spl_in->basic_in.format, pipe_ctx->plane_res.scl_data.format); in translate_SPL_in_params_from_pipe_ctx()
138 // Make spl input basic output info alpha_en field point to plane res scl_data lb_params alpha_en in translate_SPL_in_params_from_pipe_ctx()
139 spl_in->basic_out.alpha_en = pipe_ctx->plane_res.scl_data.lb_params.alpha_en; in translate_SPL_in_params_from_pipe_ctx()
197 spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; in translate_SPL_in_params_from_pipe_ctx()
198 spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; in translate_SPL_in_params_from_pipe_ctx()
218 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); in translate_SPL_out_params_to_pipe_ctx()
220 populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios); in translate_SPL_out_params_to_pipe_ctx()
222 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport); in translate_SPL_out_params_to_pipe_ctx()
224 populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data in translate_SPL_out_params_to_pipe_ctx()
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data in pipe_ctx_to_e2e_pipe_params()
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c1165 struct scaler_data *scl_data, in dce_transform_get_optimal_number_of_taps() argument
1169 int pixel_width = scl_data->viewport.width; in dce_transform_get_optimal_number_of_taps()
1173 (scl_data->viewport.width > scl_data->recout.width)) in dce_transform_get_optimal_number_of_taps()
1174 pixel_width = scl_data->recout.width; in dce_transform_get_optimal_number_of_taps()
1178 scl_data->lb_params.depth, in dce_transform_get_optimal_number_of_taps()
1194 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps()
1195 scl_data->taps.v_taps = decide_taps(scl_data in dce_transform_get_optimal_number_of_taps()
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1119 pipe_ctx->plane_res.scl_data.recout = shift_rec( in calculate_recout()
1123 &pipe_ctx->plane_res.scl_data.recout, in calculate_recout()
1127 memset(&pipe_ctx->plane_res.scl_data.recout, 0, in calculate_recout()
1148 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1151 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
1156 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
1158 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
1160 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
1161 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
1162 pipe_ctx->plane_res.scl_data in calculate_scaling_ratios()
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/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_transform_v.c48 const struct scaler_data *scl_data, in calculate_viewport() argument
53 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport()
54 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport()
56 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport()
58 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport()
64 if (scl_data in calculate_viewport()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dtransform.h173 const struct scaler_data *scl_data);
182 struct scaler_data *scl_data,
286 const struct scaler_data *scl_data,
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_trace.h439 __entry->recout_x = plane_res->scl_data.recout.x;
440 __entry->recout_y = plane_res->scl_data.recout.y;
441 __entry->recout_w = plane_res->scl_data.recout.width;
442 __entry->recout_h = plane_res->scl_data.recout.height;
443 __entry->viewport_x = plane_res->scl_data.viewport.x;
444 __entry->viewport_y = plane_res->scl_data.viewport.y;
445 __entry->viewport_w = plane_res->scl_data.viewport.width;
446 __entry->viewport_h = plane_res->scl_data.viewport.height;
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c2935 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
2936 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP; in update_scaler()
2939 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in update_scaler()
3029 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; in dcn10_update_dchubp_dpp()
3053 &pipe_ctx->plane_res.scl_data.viewport, in dcn10_update_dchubp_dpp()
3054 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn10_update_dchubp_dpp()
3616 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn10_set_cursor_position()
3617 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn10_set_cursor_position()
3618 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn10_set_cursor_position()
3633 if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data in dcn10_set_cursor_position()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1497 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1515 &pipe_ctx->plane_res.scl_data); in program_scaler()
1715 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_apply_single_controller_ctx_to_hw()
2552 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in set_default_colors()
2559 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in set_default_colors()
2950 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in dce110_program_front_end_for_pipe()
3009 pipe_ctx->plane_res.scl_data.viewport.width, in dce110_program_front_end_for_pipe()
3010 pipe_ctx->plane_res.scl_data.viewport.height, in dce110_program_front_end_for_pipe()
3011 pipe_ctx->plane_res.scl_data.viewport.x, in dce110_program_front_end_for_pipe()
3012 pipe_ctx->plane_res.scl_data in dce110_program_front_end_for_pipe()
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/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c830 temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; in get_scaler_data_for_plane()
839 return &temp_pipe->plane_res.scl_data; in get_scaler_data_for_plane()
1232 mcache_pipe_config->plane0.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x; in dml21_get_pipe_mcache_config()
1233 mcache_pipe_config->plane0.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width; in dml21_get_pipe_mcache_config()
1235 mcache_pipe_config->plane1.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport_c.x; in dml21_get_pipe_mcache_config()
1236 mcache_pipe_config->plane1.viewport_width = pipe_ctx->plane_res.scl_data.viewport_c.width; in dml21_get_pipe_mcache_config()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1067 .viewport = pipe_ctx->plane_res.scl_data.viewport, in dcn401_set_cursor_position()
1068 .recout = pipe_ctx->plane_res.scl_data.recout, in dcn401_set_cursor_position()
1069 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn401_set_cursor_position()
1070 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn401_set_cursor_position()
1089 if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) || in dcn401_set_cursor_position()
1090 (pipe_ctx->plane_state->src_rect.height != pipe_ctx->plane_res.scl_data.viewport.height)) { in dcn401_set_cursor_position()
1174 bottom_pipe_x_pos = x_pos - pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
1176 x_pos = pipe_ctx->plane_res.scl_data.recout.x; in dcn401_set_cursor_position()
2555 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeo in dcn401_detect_pipe_changes()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c273 pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
274 pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()
275 pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; in populate_pipe_ctx_dlg_params_from_dml()
276 pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; in populate_pipe_ctx_dlg_params_from_dml()

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