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Searched refs:regWBIF_SMU_WM_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h1315 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_5_0_offset.h2204 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_6_0_offset.h1341 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_1_2_offset.h1552 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_1_4_offset.h2445 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_2_1_offset.h1169 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_5_1_offset.h2183 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_4_1_0_offset.h1179 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_1_6_offset.h1768 #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 macro
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