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Searched refs:regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h6637 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 macro
H A Ddpcs_4_2_0_offset.h267 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 macro
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H A Ddpcs_4_2_3_offset.h273 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 macro
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H A Ddpcs_4_2_2_offset.h256 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 macro
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/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_4_1_0_offset.h14481 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX global() macro
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