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Searched refs:regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h6659 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h12501 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_6_0_offset.h5653 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h6900 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h13567 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h5201 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h12480 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5741 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h7120 #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX … macro