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Searched refs:regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h2805 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 macro
H A Dgc_9_4_3_offset.h5023 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 macro
H A Dgc_12_0_0_offset.h4335 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 macro
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H A Dgc_11_0_3_offset.h7203 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 macro
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H A Dgc_11_0_0_offset.h6903 #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 macro
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