| /linux/drivers/net/phy/ |
| H A D | adin1100.c | 108 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL, in adin_config_aneg()
117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
224 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
236 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN); in adin_soft_reset()
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| H A D | nxp-c45-tja11xx.c | 824 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
836 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
845 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
1201 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
1210 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1215 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1246 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1317 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_start()
1385 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
[all …]
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| H A D | dp83td510.c | 482 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
644 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
654 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in dp83td510_cable_test_start()
709 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
714 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG, in dp83td510_cable_test_start()
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| H A D | phy-c45.c | 71 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
347 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
1261 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
1266 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
1272 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1433 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
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| H A D | marvell10g.c | 306 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
329 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
612 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
665 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
1337 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1366 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
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| H A D | microchip_t1.c | 1128 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_sgmii_init()
1144 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, in lan887x_sgmii_init()
1150 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG, in lan887x_sgmii_init()
1400 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, in lan887x_100M_setup()
1417 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, in lan887x_1000M_setup()
2086 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_get_sqi()
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| H A D | dp83822.c | 568 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_init()
629 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_init()
650 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, in dp8382x_config_rmii_mode()
672 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, in dp83826_config_init()
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| H A D | mxl-gpy.c | 721 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
728 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
735 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
748 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
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| H A D | marvell-88x2222.c | 70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, in mv2222_tx_disable()
100 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_enable_aneg()
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| H A D | marvell-88q2xxx.c | 605 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in mv88q2xxx_suspend()
830 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_init()
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| H A D | dp83tc811.c | 381 phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, in dp83811_resume()
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| H A D | dp83867.c | 494 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
853 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
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| H A D | microchip_rds_ptp.c | 54 return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val); in mchp_rds_phy_set_bits_mmd()
1075 return phy_set_bits_mmd(clock->phydev, PTP_MMD(clock), reg, in mchp_rds_ptp_top_config_intr()
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| H A D | dp83869.c | 513 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, in dp83869_config_port_mirroring()
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| H A D | as21xxx.c | 628 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK, in as21xxx_probe()
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| H A D | nxp-c45-tja11xx-macsec.c | 1612 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_macsec_config_init()
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| /linux/drivers/net/phy/mediatek/ |
| H A D | mtk-ge-soc.c | 394 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
650 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
654 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, in tx_vcm_cal_sw()
665 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
676 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
687 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
698 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
984 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
1012 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, in mt798x_phy_eee()
1021 phy_set_bits_mmd(phyde in mt798x_phy_eee()
[all...] |
| H A D | mtk-2p5ge.c | 277 phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, in mt798x_2p5ge_phy_probe()
281 phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, in mt798x_2p5ge_phy_probe()
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| /linux/drivers/net/phy/qcom/ |
| H A D | qca808x.c | 205 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, in qca808x_config_init()
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| H A D | qcom-phy-lib.c | 710 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_CTRL, in qcom_phy_counter_config()
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| H A D | qca807x.c | 668 ret = phy_set_bits_mmd(phydev, in qca807x_sfp_insert()
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| /linux/include/linux/ |
| H A D | phy.h | 1589 * phy_set_bits_mmd - Convenience function for setting bits in a register
1596 static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, in phy_set_bits_mmd() function
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