Searched refs:num_memclk_levels (Results 1 – 11 of 11) sorted by relevance
1038 &num_entries_per_clk->num_memclk_levels); in dcn32_get_memclk_states_from_smu() 1043 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1; in dcn32_get_memclk_states_from_smu() 1050 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { in dcn32_get_memclk_states_from_smu() 1051 num_levels = num_entries_per_clk->num_memclk_levels; in dcn32_get_memclk_states_from_smu() 1056 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; in dcn32_get_memclk_states_from_smu()
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 327 (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels && in dcn401_is_dc_mode_present() 1387 &num_entries_per_clk->num_memclk_levels); in dcn401_get_memclk_states_from_smu() 1388 if (num_entries_per_clk->num_memclk_levels) { in dcn401_get_memclk_states_from_smu() 1390 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; in dcn401_get_memclk_states_from_smu() 1394 if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz == in dcn401_get_memclk_states_from_smu() 1395 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz) in dcn401_get_memclk_states_from_smu() 1407 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { in dcn401_get_memclk_states_from_smu() 1408 num_levels = num_entries_per_clk->num_memclk_levels; in dcn401_get_memclk_states_from_smu()
170 unsigned int num_memclk_levels; member
535 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) { in dml2_init_soc_states()
132 unsigned int num_memclk_levels; member
417 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn351_update_bw_bounding_box_fpu()
384 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn35_update_bw_bounding_box_fpu()
2517 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; in dcn32_calculate_wm_and_dlg_fpu() 2861 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states() 3326 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn32_update_bw_bounding_box_fpu() 3327 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn32_update_bw_bounding_box_fpu() 3353 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu() 3605 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn32_override_min_req_memclk()
146 if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { in override_dml_init_with_values_from_smu() 147 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in override_dml_init_with_values_from_smu()
1025 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1757 for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { in dcn401_get_power_profile()