Searched refs:num_entries_per_clk (Results 1 – 11 of 11) sorted by relevance
82 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 98 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 219 struct clk_limit_num_entries *num_entries_per_clk; in dcn401_init_clocks() local 225 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn401_init_clocks() 1378 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; dcn401_get_memclk_states_from_smu() local [all...]
166 struct clk_limit_num_entries *num_entries_per_clk; in dcn32_init_clocks() local 172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks() 193 &num_entries_per_clk->num_dcfclk_levels); in dcn32_init_clocks() 199 &num_entries_per_clk->num_socclk_levels); in dcn32_init_clocks() 206 &num_entries_per_clk->num_dtbclk_levels); in dcn32_init_clocks() 214 &num_entries_per_clk->num_dispclk_levels); in dcn32_init_clocks() 215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks() 224 &num_entries_per_clk->num_dppclk_levels); in dcn32_init_clocks() 225 num_levels = num_entries_per_clk in dcn32_init_clocks() 1029 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; dcn32_get_memclk_states_from_smu() local [all...]
407 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn351_update_bw_bounding_box_fpu() 409 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn351_update_bw_bounding_box_fpu() 411 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn351_update_bw_bounding_box_fpu() 413 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn351_update_bw_bounding_box_fpu() 415 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn351_update_bw_bounding_box_fpu() 417 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn351_update_bw_bounding_box_fpu() 419 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn351_update_bw_bounding_box_fpu()
374 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn35_update_bw_bounding_box_fpu() 376 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn35_update_bw_bounding_box_fpu() 378 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn35_update_bw_bounding_box_fpu() 380 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn35_update_bw_bounding_box_fpu() 382 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn35_update_bw_bounding_box_fpu() 384 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn35_update_bw_bounding_box_fpu() 386 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn35_update_bw_bounding_box_fpu()
100 if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { in override_dml_init_with_values_from_smu() 101 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in override_dml_init_with_values_from_smu() 123 if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { in override_dml_init_with_values_from_smu() 124 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in override_dml_init_with_values_from_smu() 146 if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { in override_dml_init_with_values_from_smu() 147 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in override_dml_init_with_values_from_smu() 169 if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { in override_dml_init_with_values_from_smu() 170 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in override_dml_init_with_values_from_smu() 192 if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { in override_dml_init_with_values_from_smu() 193 dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk in override_dml_init_with_values_from_smu() [all...]
2517 int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; in dcn32_calculate_wm_and_dlg_fpu() 2861 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states() 2862 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; in build_synthetic_soc_states() 3320 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn32_update_bw_bounding_box_fpu() 3321 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn32_update_bw_bounding_box_fpu() 3323 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn32_update_bw_bounding_box_fpu() 3324 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; in dcn32_update_bw_bounding_box_fpu() 3326 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn32_update_bw_bounding_box_fpu() 3327 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn32_update_bw_bounding_box_fpu() 3329 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk in dcn32_update_bw_bounding_box_fpu() [all...]
1021 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params() 1022 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params() 1023 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params() 1024 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params() 1025 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled; in dcn35_clk_mgr_helper_populate_bw_params() 1026 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
179 struct dml2_clks_num_entries num_entries_per_clk; member
522 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) { in dml2_init_soc_states() 530 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) { in dml2_init_soc_states() 535 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) { in dml2_init_soc_states() 540 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) { in dml2_init_soc_states() 545 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) { in dml2_init_soc_states() 551 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) { in dml2_init_soc_states()
144 struct clk_limit_num_entries num_entries_per_clk; member
1757 for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { in dcn401_get_power_profile()