Searched refs:num_dtbclk_levels (Results 1 – 9 of 9) sorted by relevance
109 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 265 &num_entries_per_clk->num_dtbclk_levels); in dcn401_init_clocks() 267 if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz == in dcn401_init_clocks() 268 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz) in dcn401_init_clocks() 287 num_entries_per_clk->num_dtbclk_levels && in dcn401_init_clocks() 323 (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels && in dcn401_is_dc_mode_present()
172 unsigned int num_dtbclk_levels; member
545 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) { in dml2_init_soc_states()
134 unsigned int num_dtbclk_levels; member
206 &num_entries_per_clk->num_dtbclk_levels); in dcn32_init_clocks() 232 num_entries_per_clk->num_dtbclk_levels && in dcn32_init_clocks()
419 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn351_update_bw_bounding_box_fpu()
386 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn35_update_bw_bounding_box_fpu()
215 if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { in override_dml_init_with_values_from_smu() 216 dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; in override_dml_init_with_values_from_smu()
3332 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn32_update_bw_bounding_box_fpu() 3333 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; in dcn32_update_bw_bounding_box_fpu() 3365 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()