| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 39 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in rv1_determine_dppclk_threshold() argument
41 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in rv1_determine_dppclk_threshold()
42 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
43 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; in rv1_determine_dppclk_threshold()
50 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
55 if (new_clocks->dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
56 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
60 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
69 return new_clocks in rv1_determine_dppclk_threshold()
88 ramp_up_dispclk_with_dpp(struct clk_mgr_internal * clk_mgr,struct dc * dc,struct dc_clocks * new_clocks,bool safe_to_lower) ramp_up_dispclk_with_dpp() argument
194 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; rv1_update_clocks() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 297 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in dcn32_update_dppclk_dispclk_freq() argument
302 if (new_clocks->dppclk_khz) { in dcn32_update_dppclk_dispclk_freq()
304 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; in dcn32_update_dppclk_dispclk_freq()
305 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; in dcn32_update_dppclk_dispclk_freq()
307 if (new_clocks->dispclk_khz > 0) { in dcn32_update_dppclk_dispclk_freq()
309 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; in dcn32_update_dppclk_dispclk_freq()
310 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; in dcn32_update_dppclk_dispclk_freq()
506 struct dc_clocks *new_clocks, in dcn32_auto_dpm_test_log() argument
538 dramclk_khz_override = new_clocks->dramclk_khz; in dcn32_auto_dpm_test_log()
539 fclk_khz_override = new_clocks in dcn32_auto_dpm_test_log()
626 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; dcn32_update_clocks() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 344 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_notify_host_router_bw() local
369 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i]; in dcn35_notify_host_router_bw()
370 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) { in dcn35_notify_host_router_bw()
371 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i]; in dcn35_notify_host_router_bw()
372 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]); in dcn35_notify_host_router_bw()
383 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn35_update_clocks() local
395 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) in dcn35_update_clocks()
396 new_clocks->ref_dtbclk_khz = 600000; in dcn35_update_clocks()
403 if (new_clocks in dcn35_update_clocks()
1115 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; dcn35_update_clocks_fpga() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 411 struct dc_clocks *new_clocks, in dcn401_auto_dpm_test_log() argument
440 dramclk_khz_override = new_clocks->dramclk_khz; in dcn401_auto_dpm_test_log()
441 fclk_khz_override = new_clocks->fclk_khz; in dcn401_auto_dpm_test_log()
445 if (!new_clocks->p_state_change_support) in dcn401_auto_dpm_test_log()
448 if (!new_clocks->fclk_p_state_change_support) in dcn401_auto_dpm_test_log()
461 new_clocks->dramclk_khz > 0 && in dcn401_auto_dpm_test_log()
462 new_clocks->fclk_khz > 0 && in dcn401_auto_dpm_test_log()
463 new_clocks->dcfclk_khz > 0 && in dcn401_auto_dpm_test_log()
464 new_clocks->dppclk_khz > 0) { in dcn401_auto_dpm_test_log()
506 new_clocks in dcn401_auto_dpm_test_log()
767 dcn401_build_update_bandwidth_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower) dcn401_build_update_bandwidth_clocks_sequence() argument
1080 dcn401_build_update_display_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower) dcn401_build_update_display_clocks_sequence() argument
1332 struct dc_clocks new_clocks; dcn401_set_hard_min_memclk() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 198 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks() local
232 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn3_update_clocks()
233 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn3_update_clocks()
235 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
236 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn3_update_clocks()
240 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn3_update_clocks()
241 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()
245 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn3_update_clocks()
247 clk_mgr_base->clks.socclk_khz = new_clocks in dcn3_update_clocks()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 141 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn316_update_clocks() local
155 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn316_update_clocks()
157 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn316_update_clocks()
159 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks()
176 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { in dcn316_update_clocks()
178 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks()
190 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn316_update_clocks()
191 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn316_update_clocks()
196 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn316_update_clocks()
197 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks in dcn316_update_clocks()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 131 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn315_update_clocks() local
141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks()
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks()
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn315_update_clocks()
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
167 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { in dcn315_update_clocks()
169 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
181 if (!new_clocks->p_state_change_support) in dcn315_update_clocks()
182 new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK; in dcn315_update_clocks()
183 if (should_set_clock(safe_to_lower, new_clocks in dcn315_update_clocks()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 211 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn314_update_clocks() local
226 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && in dcn314_update_clocks()
227 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn314_update_clocks()
228 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); in dcn314_update_clocks()
230 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn314_update_clocks()
233 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn314_update_clocks()
235 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn314_update_clocks()
252 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && in dcn314_update_clocks()
253 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn314_update_clocks()
256 clk_mgr_base->clks.zstate_support = new_clocks in dcn314_update_clocks()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 136 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks() local
174 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
175 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rn_update_clocks()
180 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in rn_update_clocks()
181 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in rn_update_clocks()
187 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) in rn_update_clocks()
188 new_clocks->dppclk_khz = 100000; in rn_update_clocks()
194 if (new_clocks->dppclk_khz == 0 || new_clocks in rn_update_clocks()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 100 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in vg_update_clocks() local
142 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) { in vg_update_clocks()
143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()
148 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) { in vg_update_clocks()
149 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in vg_update_clocks()
154 if (new_clocks->dppclk_khz < 100000) in vg_update_clocks()
155 new_clocks->dppclk_khz = 100000; in vg_update_clocks()
157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks()
160 clk_mgr_base->clks.dppclk_khz = new_clocks in vg_update_clocks()
[all...] |
| /linux/sound/isa/ |
| H A D | es18xx.c | 353 static const struct snd_ratnum new_clocks[2] = { variable
370 .rats = new_clocks,
401 if (runtime->rate_num == new_clocks[0].num) in snd_es18xx_rate_set()
|