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Searched refs:mmVGA_CACHE_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h36 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
H A Ddcn_3_0_1_offset.h167 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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H A Ddcn_1_0_offset.h407 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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H A Ddcn_2_1_0_offset.h111 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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H A Ddcn_3_0_2_offset.h51 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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H A Ddcn_2_0_0_offset.h51 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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H A Ddcn_3_0_0_offset.h33 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h573 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 macro
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