| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_dp_mst_helper_test.c | 73 int lane_count; member
86 * .expected = .link_rate * .lane_count * 0.9671 / 8 / 54 / 100
88 * .expected = .link_rate * .lane_count * 0.8000 / 8 / 54 / 100
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_fixed_vs_pe_retimer.c | 75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
254 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence()
296 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence()
305 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) { in dp_perform_fixed_vs_pe_training_sequence()
326 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
377 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
415 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
447 status = dp_get_cr_failure(lane_count, dpcd_lane_statu in dp_perform_fixed_vs_pe_training_sequence()
455 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; dp_perform_fixed_vs_pe_training_sequence() local
[all...] |
| H A D | link_dp_capability.c | 67 enum dc_lane_count lane_count; member
102 .lane_count = LANE_COUNT_ONE,
471 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument
473 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count()
481 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument
483 switch (lane_count) { in reduce_lane_count()
530 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument
532 switch (lane_count) { in increase_lane_count()
602 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count in decide_fallback_link_setting_max_bw_policy()
[all...] |
| H A D | link_dp_training.c | 172 lt_settings->link_settings.lane_count, in dp_log_training_result()
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
467 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
570 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_check_link_loss_status()
631 (uint32_t)(link_training_setting->link_settings.lane_count); in dp_get_lane_status_and_lane_adjust()
1102 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1159 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1169 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1194 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1270 size_in_bytes = lt_settings->link_settings.lane_count * in dpcd_set_lt_pattern_and_lane_settings()
1420 enum dc_lane_count lane_count = perform_post_lt_adj_req_sequence() local
[all...] |
| H A D | link_dp_irq_handler.c | 60 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
66 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
280 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
281 link->verified_link_cap.lane_count; in dp_handle_link_loss()
403 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
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| H A D | link_dp_training_fixed_vs_pe_retimer.h | 39 uint8_t lane_count);
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_core.c | 230 int lane, lane_count, retval; in analogix_dp_link_start() local
232 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
237 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
252 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
256 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
284 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
289 lane_count); in analogix_dp_link_start()
304 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
318 analogix_dp_channel_eq_ok(u8 link_status[2],u8 link_align,int lane_count) analogix_dp_channel_eq_ok() argument
366 int lane, lane_count; analogix_dp_get_adjust_training_lane() local
389 int lane, lane_count, retval; analogix_dp_process_clock_recovery() local
455 int lane_count, retval; analogix_dp_process_equalizer_training() local
541 analogix_dp_get_max_rx_lane_count(struct analogix_dp_device * dp,u8 * lane_count) analogix_dp_get_max_rx_lane_count() argument
[all...] |
| /linux/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.h | 83 * @lane_count: lane count requested by the sink
87 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
89 return (lane_count == 1 || in is_lane_count_valid()
90 lane_count == 2 || in is_lane_count_valid()
91 lane_count == 4); in is_lane_count_valid()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp.h | 53 int link_rate, int lane_count);
107 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
108 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
140 u32 link_clock, u32 lane_count,
158 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
160 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
206 u8 lane_count);
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| H A D | intel_dpio_phy.c | 318 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
327 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
342 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
597 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_dpio_phy_calc_lane_lat_optim_mask() argument
599 switch (lane_count) { in bxt_dpio_phy_calc_lane_lat_optim_mask()
607 MISSING_CASE(lane_count); in bxt_dpio_phy_calc_lane_lat_optim_mask()
736 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
749 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
757 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
765 for (i = 0; i < crtc_state->lane_count; in chv_set_phy_signal_level()
[all...] |
| H A D | vlv_dsi.c | 57 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
61 8 * 100), lane_count); in txbyteclkhs()
65 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
68 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1019 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1071 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1073 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1075 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1127 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1222 unsigned int lane_count = intel_dsi->lane_count; set_dsi_timings() local
[all...] |
| H A D | intel_combo_phy.c | 262 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
269 switch (lane_count) { in intel_combo_phy_power_up_lanes()
280 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
287 switch (lane_count) { in intel_combo_phy_power_up_lanes()
297 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
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| H A D | intel_dp_mst.c | 192 overhead = drm_dp_bw_overhead(crtc_state->lane_count, in intel_dp_mst_bw_overhead()
214 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, in intel_dp_mst_compute_m_n()
291 crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
382 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
406 4 / crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
446 crtc_state->lane_count = limits->max_lane_count; in mst_stream_compute_link_config()
510 crtc_state->lane_count = limits->max_lane_count; in mst_stream_dsc_compute_link_config()
729 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in mst_stream_compute_config()
1161 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument
1164 intel_dp->link.mst_probed_lane_count == lane_count; in intel_mst_probed_link_params_valid()
1168 intel_mst_set_probed_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count) intel_mst_set_probed_link_params() argument
2080 int lane_count = intel_dp_max_lane_count(intel_dp); intel_dp_mst_prepare_probe() local
[all...] |
| H A D | vlv_dsi_pll.c | 50 int lane_count) in dsi_clk_from_pclk() argument
57 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
170 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
185 intel_dsi->lane_count); in vlv_dsi_pll_compute()
351 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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| H A D | intel_dp.c | 407 int lane_count; in intel_dp_max_lane_count() local
410 lane_count = forced_lane_count(intel_dp); in intel_dp_max_lane_count()
412 lane_count = intel_dp->link.max_lane_count; in intel_dp_max_lane_count()
414 switch (lane_count) { in intel_dp_max_lane_count()
418 return lane_count; in intel_dp_max_lane_count()
420 MISSING_CASE(lane_count); in intel_dp_max_lane_count()
746 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) in intel_dp_link_config_get() argument
757 *lane_count = intel_dp_link_config_lane_count(lc); in intel_dp_link_config_get()
760 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) in intel_dp_link_config_index() argument
764 int lane_count_exp = ilog2(lane_count); in intel_dp_link_config_index()
801 intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count) intel_dp_link_params_valid() argument
961 intel_dp_dsc_get_max_compressed_bpp(struct intel_display * display,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay,int num_joined_pipes,enum intel_output_format output_format,u32 pipe_bpp,u32 timeslots) intel_dp_dsc_get_max_compressed_bpp() argument
1775 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); intel_dp_compute_link_config_wide() local
1957 is_bw_sufficient_for_dsc_config(int dsc_bpp_x16,u32 link_clock,u32 lane_count,u32 mode_clock,enum intel_output_format output_format,int timeslots) is_bw_sufficient_for_dsc_config() argument
1977 int link_rate, lane_count; dsc_compute_link_config() local
3310 intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count) intel_dp_set_link_params() argument
[all...] |
| H A D | intel_combo_phy.h | 18 int lane_count, bool lane_reversal);
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| H A D | intel_dpio_phy.h | 40 u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
102 static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_dpio_phy_calc_lane_lat_optim_mask() argument
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 262 uint8_t lane_count; member
896 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
909 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
911 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
915 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
919 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
927 intel_dp->lane_count in cdv_intel_dp_mode_fixup()
989 int lane_count = 4, bpp = 24; cdv_intel_dp_set_m_n() local
1313 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE],int lane_count) cdv_intel_clock_recovery_ok() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 263 return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000; in dp_link_bandwidth_kbps()
299 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN) in dp_validate_mode_timing()
488 enum dc_lane_count lane_count, in get_av_stream_map_lane_count() argument
495 av_stream_map_lane_count = lane_count; in get_av_stream_map_lane_count()
509 enum dc_lane_count lane_count, in get_audio_sdp_overhead() argument
518 audio_sdp_overhead = lane_count * 2 + 8; in get_audio_sdp_overhead()
559 const uint32_t lane_count = 4; in dp_required_hblank_size_bytes() local
565 link_encoding, lane_count, is_mst); in dp_required_hblank_size_bytes()
567 link_encoding, lane_count, is_mst); in dp_required_hblank_size_bytes()
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dp.c | 74 int lane_count; member
1257 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1264 .lanes = lane_count, in mtk_dp_phy_configure()
1428 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data()
1450 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1483 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1521 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1818 u8 lane_count, link_rate, train_limit, max_link_rate; in mtk_dp_training() local
1823 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training()
1836 ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count); in mtk_dp_training()
[all...] |
| /linux/include/drm/display/ |
| H A D | drm_dp_helper.h | 37 int lane_count);
39 int lane_count);
62 int lane_count);
64 int lane_count);
981 int drm_dp_bw_overhead(int lane_count, int hactive,
988 int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
| H A D | dcn31_dio_link_encoder.c | 475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
659 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
681 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
|
| /linux/drivers/gpu/drm/bridge/ |
| H A D | ite-it6505.c | 453 u8 lane_count; member
812 switch (it6505->lane_count) { in it6505_lane_termination_on()
824 switch (it6505->lane_count) { in it6505_lane_termination_on()
856 GENMASK(7, 8 - it6505->lane_count) : in it6505_lane_power_on()
857 GENMASK(3 + it6505->lane_count, 4)) | in it6505_lane_power_on()
1365 it6505->lane_count = MAX_LANE_COUNT; in it6505_variable_config()
1669 it6505->lane_count = link->num_lanes; in it6505_parse_link_capabilities()
1671 it6505->lane_count); in it6505_parse_link_capabilities()
1672 it6505->lane_count = min_t(int, it6505->lane_count, in it6505_parse_link_capabilities()
1826 it6505_check_max_voltage_swing_reached(u8 * lane_voltage_swing,u8 lane_count) it6505_check_max_voltage_swing_reached() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_link_encoder.c | 63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap()
64 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()
|