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Searched refs:inbox1 (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_srv.c661 struct dmub_region inbox1, outbox1, outbox0; in dmub_srv_hw_init() local
727 inbox1.base = cw4.region.base; in dmub_srv_hw_init()
728 inbox1.top = cw4.region.base + DMUB_RB_SIZE; in dmub_srv_hw_init()
729 outbox1.base = inbox1.top; in dmub_srv_hw_init()
730 outbox1.top = inbox1.top + DMUB_RB_SIZE; in dmub_srv_hw_init()
762 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); in dmub_srv_hw_init()
774 dmub_rb_init(&dmub->inbox1.rb, &rb_params); in dmub_srv_hw_init()
815 dmub->inbox1.rb.wrpt = 0; in dmub_srv_hw_reset()
816 dmub->inbox1.rb.rptr = 0; in dmub_srv_hw_reset()
817 dmub->inbox1 in dmub_srv_hw_reset()
960 const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; dmub_srv_wait_for_pending() local
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H A Ddmub_dcn20.c275 const struct dmub_region *inbox1) in dmub_dcn20_setup_mailbox() argument
279 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); in dmub_dcn20_setup_mailbox()
283 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); in dmub_dcn20_setup_mailbox()
H A Ddmub_dcn31.c245 const struct dmub_region *inbox1) in dmub_dcn31_setup_mailbox() argument
247 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); in dmub_dcn31_setup_mailbox()
248 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); in dmub_dcn31_setup_mailbox()
H A Ddmub_dcn35.c281 const struct dmub_region *inbox1) in dmub_dcn35_setup_mailbox() argument
283 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); in dmub_dcn35_setup_mailbox()
284 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); in dmub_dcn35_setup_mailbox()
H A Ddmub_dcn32.c269 const struct dmub_region *inbox1) in dmub_dcn32_setup_mailbox() argument
271 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); in dmub_dcn32_setup_mailbox()
272 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); in dmub_dcn32_setup_mailbox()
H A Ddmub_dcn401.c261 const struct dmub_region *inbox1) in dmub_dcn401_setup_mailbox() argument
263 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); in dmub_dcn401_setup_mailbox()
264 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); in dmub_dcn401_setup_mailbox()
H A Ddmub_dcn20.h204 const struct dmub_region *inbox1);
H A Ddmub_dcn31.h206 const struct dmub_region *inbox1);
H A Ddmub_dcn32.h213 const struct dmub_region *inbox1);
H A Ddmub_dcn35.h226 const struct dmub_region *inbox1);
H A Ddmub_dcn401.h223 const struct dmub_region *inbox1);
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c198 dmub_rb_num_free(&dmub->inbox1.rb) >= count - i) { in dc_dmub_srv_fb_cmd_list_queue_execute()
1443 "resync inbox1 (ips1_commit=%u ips2_commit=%u)", in dc_dmub_srv_exit_low_power_state()