| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | soc15_common.h | 40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ argument
146 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
148 #define RREG32_RLC_NO_KIQ(reg, hwip) \ argument
149 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
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| H A D | amdgpu_aca.c | 184 struct aca_hwip *hwip; in aca_bank_hwip_is_matched() local
191 hwip = &aca_hwid_mcatypes[type]; in aca_bank_hwip_is_matched()
192 if (!hwip->hwid) in aca_bank_hwip_is_matched()
199 return hwip->hwid == hwid && hwip->mcatype == mcatype; in aca_bank_hwip_is_matched()
208 return handle->hwip == ACA_HWIP_TYPE_UMC; in aca_bank_is_valid()
210 if (!aca_bank_hwip_is_matched(bank, handle->hwip)) in aca_bank_is_valid()
653 handle->hwip = ras_info->hwip; in add_aca_handle()
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| H A D | amdgpu_virt.h | 430 u32 acc_flags, u32 hwip, u32 xcc_id);
432 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
439 u32 acc_flags, u32 hwip,
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| H A D | amdgpu_imu.h | 42 u32 hwip; member
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| H A D | amdgpu_aca.h | 173 enum aca_hwip_type hwip; member
208 enum aca_hwip_type hwip; member
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| H A D | amdgpu_ras.h | 386 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ argument
387 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
397 uint32_t hwip; member
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| H A D | amdgpu_virt.c | 1016 u32 acc_flags, u32 hwip, in amdgpu_virt_get_rlcg_reg_access_flag() argument
1021 switch (hwip) { in amdgpu_virt_get_rlcg_reg_access_flag()
1147 u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_wreg() argument
1155 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { in amdgpu_sriov_wreg()
1167 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_rreg() argument
1175 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) in amdgpu_sriov_rreg()
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| H A D | imu_v11_0_3.c | 117 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_rlc_ram_register_setting()
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| H A D | soc24.c | 177 if (!adev->reg_offset[en->hwip][en->inst]) in soc24_read_register()
179 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc24_read_register()
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| H A D | soc21.c | 311 if (!adev->reg_offset[en->hwip][en->inst]) in soc21_read_register()
313 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
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| H A D | nv.c | 396 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
398 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
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| H A D | imu_v11_0.c | 334 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_imu_rlc_ram()
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| H A D | imu_v12_0.c | 267 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_imu_rlc_ram_old()
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| H A D | umc_v12_0.c | 503 .hwip = ACA_HWIP_TYPE_UMC,
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| H A D | mmhub_v1_8.c | 840 .hwip = ACA_HWIP_TYPE_SMU,
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| H A D | amdgpu_ras.c | 4889 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_memory_id_field()
4913 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_err_cnt_field()
4990 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, in amdgpu_ras_inst_reset_ras_error_count()
4993 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, in amdgpu_ras_inst_reset_ras_error_count()
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| H A D | jpeg_v5_0_1.c | 1048 .hwip = ACA_HWIP_TYPE_SMU,
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| H A D | jpeg_v4_0_3.c | 1443 .hwip = ACA_HWIP_TYPE_SMU,
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| H A D | amdgpu.h | 147 u32 hwip; member
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| H A D | amdgpu_xgmi.c | 1219 .hwip = ACA_HWIP_TYPE_PCS_XGMI,
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| H A D | vcn_v5_0_1.c | 1588 .hwip = ACA_HWIP_TYPE_SMU,
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| H A D | gfx_v9_4_3.c | 915 .hwip = ACA_HWIP_TYPE_SMU,
1710 adev, entry->hwip, entry->instance) : in gfx_v9_4_3_check_rlcg_range()
1712 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + in gfx_v9_4_3_check_rlcg_range()
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| H A D | vcn_v4_0_3.c | 2120 .hwip = ACA_HWIP_TYPE_SMU,
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | common_baco.h | 47 uint32_t hwip; member
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| H A D | common_baco.c | 112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] in soc15_baco_program_registers()
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