Searched refs:ctrl3 (Results 1 – 6 of 6) sorted by relevance
459 /* Dump FMD ctrl3. The ctrl3 input is in host byte order */460 static void spu2_dump_fmd_ctrl3(u64 ctrl3) in spu2_dump_fmd_ctrl3() argument 462 packet_log(" FMD CTRL3 %#16llx\n", ctrl3); in spu2_dump_fmd_ctrl3() 464 packet_log(" Payload length %llu bytes\n", ctrl3 & SPU2_PL_LEN); in spu2_dump_fmd_ctrl3() 466 (ctrl3 & SPU2_TLS_LEN) >> SPU2_TLS_LEN_SHIFT); in spu2_dump_fmd_ctrl3() 474 spu2_dump_fmd_ctrl3(le64_to_cpu(fmd->ctrl3)); in spu2_dump_fmd() 563 u64 ctrl3; in spu2_fmd_init() local 588 ctrl3 = 0; in spu2_fmd_init() 593 fmd->ctrl3 in spu2_fmd_init() 763 u64 ctrl3; spu2_fmd_ctrl3_write() local 809 u64 ctrl3; spu2_payload_length() local 1192 u64 ctrl3; spu2_cipher_req_finish() local [all...]
79 __le64 ctrl3; member 158 /* FMD ctrl3 field masks */167 * ctrl3 word of FMD.
98 u32 ctrl2, ctrl3; in dwmac4_rx_queue_priority() local 102 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority() 112 ctrl3 &= ~clear_mask; in dwmac4_rx_queue_priority() 122 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority() 126 ctrl3 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & in dwmac4_rx_queue_priority() 129 writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3); in dwmac4_rx_queue_priority()
103 u32 ctrl2, ctrl3; in dwxgmac2_rx_queue_prio() local 107 ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio() 117 ctrl3 &= ~clear_mask; in dwxgmac2_rx_queue_prio() 127 writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio() 131 ctrl3 |= (prio << XGMAC_PSRQ_SHIFT(queue)) & in dwxgmac2_rx_queue_prio() 134 writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3); in dwxgmac2_rx_queue_prio()
4571 u32 ctrl3; in mvpp22_mode_reconfigure() local 4588 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure() 4589 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; in mvpp22_mode_reconfigure() 4592 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; in mvpp22_mode_reconfigure() 4594 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; in mvpp22_mode_reconfigure() 4596 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
111 ddr-ctrl3-thermal {