Searched refs:cp_hqd_pq_base_hi (Results 1 – 18 of 18) sorted by relevance
193 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd() 353 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
195 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
179 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
232 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
256 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
88 uint32_t cp_hqd_pq_base_hi; member
297 uint32_t cp_hqd_pq_base_hi; member
307 uint32_t cp_hqd_pq_base_hi; member
812 uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) member
813 uint32_t cp_hqd_pq_base_hi; member
1117 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v11_0_mqd_init() 1207 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v11_0_queue_init_register()
1199 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v12_0_mqd_init() 1296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v12_0_queue_init_register()
1897 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_4_3_xcc_mqd_init() 2009 mqd->cp_hqd_pq_base_hi); in gfx_v9_4_3_xcc_kiq_init_register()
3168 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v12_0_compute_mqd_init() 3299 mqd->cp_hqd_pq_base_hi); in gfx_v12_0_kiq_init_register()
3618 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_0_mqd_init() 3729 mqd->cp_hqd_pq_base_hi); in gfx_v9_0_kiq_init_register()
2859 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v7_0_mqd_init()
4444 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v8_0_mqd_init()