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Searched refs:clk_mgr_dce (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c39 (clk_mgr_dce->regs->reg)
43 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
46 clk_mgr_dce->base.ctx
133 static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz) in clk_mgr_adjust_dp_ref_freq_for_ss() argument
135 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { in clk_mgr_adjust_dp_ref_freq_for_ss()
137 dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage, in clk_mgr_adjust_dp_ref_freq_for_ss()
138 clk_mgr_dce->dprefclk_ss_divider), 200); in clk_mgr_adjust_dp_ref_freq_for_ss()
150 struct dce_clk_mgr *clk_mgr_dce in dce_get_dp_ref_freq_khz() local
176 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce12_get_dp_ref_freq_khz() local
217 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce_get_required_clocks_state() local
250 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce_set_clock() local
290 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce112_set_clock() local
343 dce_clock_read_integrated_info(struct dce_clk_mgr * clk_mgr_dce) dce_clock_read_integrated_info() argument
401 dce_clock_read_ss_info(struct dce_clk_mgr * clk_mgr_dce) dce_clock_read_ss_info() argument
470 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce121_clock_patch_xgmi_ss_info() local
676 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce_update_clocks() local
703 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce11_update_clocks() local
730 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce112_update_clocks() local
757 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); dce12_update_clocks() local
812 dce_clk_mgr_construct(struct dce_clk_mgr * clk_mgr_dce,struct dc_context * ctx,const struct clk_mgr_registers * regs,const struct clk_mgr_shift * clk_shift,const struct clk_mgr_mask * clk_mask) dce_clk_mgr_construct() argument
851 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); dce_clk_mgr_create() local
874 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); dce110_clk_mgr_create() local
899 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); dce112_clk_mgr_create() local
920 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); dce120_clk_mgr_create() local
942 struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), dce121_clk_mgr_create() local
963 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr); dce_clk_mgr_destroy() local
[all...]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c114 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz) in dce_adjust_dp_ref_freq_for_ss() argument
116 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { in dce_adjust_dp_ref_freq_for_ss()
118 dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage, in dce_adjust_dp_ref_freq_for_ss()
119 clk_mgr_dce->dprefclk_ss_divider), 200); in dce_adjust_dp_ref_freq_for_ss()
157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_get_dp_ref_freq_khz() local
159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
198 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_required_clocks_state() local
207 for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) in dce_get_required_clocks_state()
209 clk_mgr_dce in dce_get_required_clocks_state()
233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); dce_set_clock() local
277 dce_clock_read_integrated_info(struct clk_mgr_internal * clk_mgr_dce) dce_clock_read_integrated_info() argument
330 dce_clock_read_ss_info(struct clk_mgr_internal * clk_mgr_dce) dce_clock_read_ss_info() argument
406 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); dce_update_clocks() local
[all...]
H A Ddce_clk_mgr.h33 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz);
44 struct clk_mgr_internal *clk_mgr_dce);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.c72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock() local
83 clk_mgr_dce->base.dentist_vco_freq_khz / 62); in dce112_set_clock()
97 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce112_set_clock()
115 if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) in dce112_set_clock()
120 clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; in dce112_set_clock()
195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks() local
200 if (!clk_mgr_dce->dfs_bypass_active) in dce112_update_clocks()
205 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce112_update_clocks()
206 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { in dce112_update_clocks()
208 clk_mgr_dce in dce112_update_clocks()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
H A Ddce60_clk_mgr.c124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks() local
129 if (!clk_mgr_dce->dfs_bypass_active) in dce60_update_clocks()
134 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce60_update_clocks()
135 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { in dce60_update_clocks()
137 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; in dce60_update_clocks()
H A Ddce60_clk_mgr.h34 struct clk_mgr_internal *clk_mgr_dce);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce11_update_clocks() local
258 if (!clk_mgr_dce->dfs_bypass_active) in dce11_update_clocks()
263 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce11_update_clocks()
264 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { in dce11_update_clocks()
266 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; in dce11_update_clocks()