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Searched refs:amdgpu_ring_write (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c186 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_start()
188 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_start()
190 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_start()
191 amdgpu_ring_write(ring, 0x80010000); in jpeg_v1_0_decode_ring_insert_start()
205 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_insert_end()
207 amdgpu_ring_write(ring, 0x68e04); in jpeg_v1_0_decode_ring_insert_end()
209 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_insert_end()
210 amdgpu_ring_write(ring, 0x00010000); in jpeg_v1_0_decode_ring_insert_end()
230 amdgpu_ring_write(ring, in jpeg_v1_0_decode_ring_emit_fence()
232 amdgpu_ring_write(rin in jpeg_v1_0_decode_ring_emit_fence()
[all...]
H A Dvcn_sw_ring.c32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); in vcn_dec_sw_ring_emit_fence()
33 amdgpu_ring_write(ring, addr); in vcn_dec_sw_ring_emit_fence()
34 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_dec_sw_ring_emit_fence()
35 amdgpu_ring_write(ring, seq); in vcn_dec_sw_ring_emit_fence()
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); in vcn_dec_sw_ring_emit_fence()
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); in vcn_dec_sw_ring_insert_end()
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); in vcn_dec_sw_ring_emit_ib()
50 amdgpu_ring_write(ring, vmid); in vcn_dec_sw_ring_emit_ib()
51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_dec_sw_ring_emit_ib()
52 amdgpu_ring_write(rin in vcn_dec_sw_ring_emit_ib()
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H A Djpeg_v2_0.c467 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_start()
469 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_start()
471 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_start()
473 amdgpu_ring_write(ring, 0x80010000); in jpeg_v2_0_dec_ring_insert_start()
485 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_insert_end()
487 amdgpu_ring_write(ring, 0x68e04); in jpeg_v2_0_dec_ring_insert_end()
489 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in jpeg_v2_0_dec_ring_insert_end()
491 amdgpu_ring_write(ring, 0x00010000); in jpeg_v2_0_dec_ring_insert_end()
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v2_0_dec_ring_emit_fence()
511 amdgpu_ring_write(rin in jpeg_v2_0_dec_ring_emit_fence()
[all...]
H A Duvd_v6_0.c183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
484 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
485 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
488 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
489 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
492 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
493 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
496 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
497 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
499 amdgpu_ring_write(rin in uvd_v6_0_hw_init()
[all...]
H A Duvd_v5_0.c172 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
173 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
176 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
177 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
180 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
181 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
184 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
185 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
187 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
188 amdgpu_ring_write(rin in uvd_v5_0_hw_init()
[all...]
H A Duvd_v4_2.c175 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
176 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
179 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
180 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
183 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
184 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
187 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
188 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
191 amdgpu_ring_write(rin in uvd_v4_2_hw_init()
[all...]
H A Duvd_v3_1.c94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); in uvd_v3_1_ring_emit_ib()
95 amdgpu_ring_write(ring, ib->gpu_addr); in uvd_v3_1_ring_emit_ib()
96 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v3_1_ring_emit_ib()
97 amdgpu_ring_write(ring, ib->length_dw); in uvd_v3_1_ring_emit_ib()
115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
116 amdgpu_ring_write(ring, seq); in uvd_v3_1_ring_emit_fence()
117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
118 amdgpu_ring_write(ring, addr & 0xffffffff); in uvd_v3_1_ring_emit_fence()
119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v3_1_ring_emit_fence()
120 amdgpu_ring_write(rin in uvd_v3_1_ring_emit_fence()
[all...]
H A Djpeg_v4_0_3.c740 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_insert_start()
742 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ in jpeg_v4_0_3_dec_ring_insert_start()
744 amdgpu_ring_write(ring, in jpeg_v4_0_3_dec_ring_insert_start()
747 amdgpu_ring_write(ring, 0x80004000); in jpeg_v4_0_3_dec_ring_insert_start()
761 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_insert_end()
763 amdgpu_ring_write(ring, 0x62a04); in jpeg_v4_0_3_dec_ring_insert_end()
765 amdgpu_ring_write(ring, in jpeg_v4_0_3_dec_ring_insert_end()
768 amdgpu_ring_write(ring, 0x00004000); in jpeg_v4_0_3_dec_ring_insert_end()
787 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in jpeg_v4_0_3_dec_ring_emit_fence()
789 amdgpu_ring_write(rin in jpeg_v4_0_3_dec_ring_emit_fence()
[all...]
H A Duvd_v7_0.c191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
549 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
550 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
554 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
555 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
559 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
560 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
563 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
565 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
567 amdgpu_ring_write(rin in uvd_v7_0_hw_init()
[all...]
H A Damdgpu_vpe.c466 amdgpu_ring_write(ring, ring->funcs->nop | in vpe_ring_insert_nop()
469 amdgpu_ring_write(ring, ring->funcs->nop); in vpe_ring_insert_nop()
494 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | in vpe_ring_emit_pred_exec()
496 amdgpu_ring_write(ring, exec_count & 0x1fff); in vpe_ring_emit_pred_exec()
507 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | in vpe_ring_emit_ib()
511 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); in vpe_ring_emit_ib()
512 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vpe_ring_emit_ib()
513 amdgpu_ring_write(ring, ib->length_dw); in vpe_ring_emit_ib()
514 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
515 amdgpu_ring_write(rin in vpe_ring_emit_ib()
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H A Dsdma_v2_4.c231 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
234 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
257 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
262 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
263 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
264 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
284 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
287 amdgpu_ring_write(rin in sdma_v2_4_ring_emit_hdp_flush()
[all...]
H A Dsi_dma.c88 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
89 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
90 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
91 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
113 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
114 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
115 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
116 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
120 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
121 amdgpu_ring_write(rin in si_dma_ring_emit_fence()
[all...]
H A Dgfx_v7_0.c2045 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2046 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v7_0_ring_test_ring()
2047 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2088 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2089 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2092 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2093 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2094 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2095 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2096 amdgpu_ring_write(rin in gfx_v7_0_ring_emit_hdp_flush()
[all...]
H A Dsdma_v6_0.c149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v6_0_ring_init_cond_exec()
150 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
152 amdgpu_ring_write(ring, 1); in sdma_v6_0_ring_init_cond_exec()
156 amdgpu_ring_write(ring, 0); in sdma_v6_0_ring_init_cond_exec()
248 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v6_0_ring_insert_nop()
251 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v6_0_ring_insert_nop()
282 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v6_0_ring_emit_ib()
285 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
286 amdgpu_ring_write(rin in sdma_v6_0_ring_emit_ib()
[all...]
H A Dsdma_v3_0.c407 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
410 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
433 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
436 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
437 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
438 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
439 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
440 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
460 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
463 amdgpu_ring_write(rin in sdma_v3_0_ring_emit_hdp_flush()
[all...]
H A Dsdma_v7_0.c149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v7_0_ring_init_cond_exec()
150 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
152 amdgpu_ring_write(ring, 1); in sdma_v7_0_ring_init_cond_exec()
156 amdgpu_ring_write(ring, 0); in sdma_v7_0_ring_init_cond_exec()
252 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v7_0_ring_insert_nop()
255 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v7_0_ring_insert_nop()
286 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v7_0_ring_emit_ib()
289 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v7_0_ring_emit_ib()
290 amdgpu_ring_write(rin in sdma_v7_0_ring_emit_ib()
[all...]
H A Dsdma_v5_2.c148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_2_ring_init_cond_exec()
149 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
150 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
151 amdgpu_ring_write(ring, 1); in sdma_v5_2_ring_init_cond_exec()
155 amdgpu_ring_write(ring, 0); in sdma_v5_2_ring_init_cond_exec()
262 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_2_ring_insert_nop()
265 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_2_ring_insert_nop()
296 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_2_ring_emit_ib()
299 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
300 amdgpu_ring_write(rin in sdma_v5_2_ring_emit_ib()
[all...]
H A Dvcn_v1_0.c1514 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1516 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1517 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1519 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1533 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1535 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1555 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1557 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1558 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1560 amdgpu_ring_write(rin in vcn_v1_0_dec_ring_emit_fence()
[all...]
H A Dvcn_v2_0.c1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1487 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1488 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1489 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1503 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1504 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1523 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1524 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1544 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1545 amdgpu_ring_write(rin in vcn_v2_0_dec_ring_emit_fence()
[all...]
H A Dsdma_v5_0.c308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
309 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
310 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
311 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
315 amdgpu_ring_write(ring, 0); in sdma_v5_0_ring_init_cond_exec()
414 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
417 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_0_ring_emit_ib()
451 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
452 amdgpu_ring_write(rin in sdma_v5_0_ring_emit_ib()
[all...]
H A Dgfx_v8_0.c850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
852 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4147 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4148 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4150 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4151 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4152 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4157 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4160 amdgpu_ring_write(rin in gfx_v8_0_cp_gfx_start()
[all...]
H A Dgfx_v6_0.c1801 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1802 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); in gfx_v6_0_ring_test_ring()
1803 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1820 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1821 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1831 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1832 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1833 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1834 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1835 amdgpu_ring_write(rin in gfx_v6_0_ring_emit_fence()
[all...]
H A Dgfx_v9_0.c936 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
937 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
941 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
943 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
945 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx_v9_0_kiq_set_resources()
946 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx_v9_0_kiq_set_resources()
947 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
948 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_0_kiq_set_resources()
958 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_0_kiq_map_queues()
960 amdgpu_ring_write(kiq_rin in gfx_v9_0_kiq_map_queues()
[all...]
H A Dgfx_v9_4_3.c184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_4_3_kiq_set_resources()
185 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
189 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
191 amdgpu_ring_write(kiq_ring, in gfx_v9_4_3_kiq_set_resources()
193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ in gfx_v9_4_3_kiq_set_resources()
194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ in gfx_v9_4_3_kiq_set_resources()
195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_4_3_kiq_set_resources()
196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_4_3_kiq_set_resources()
207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_4_3_kiq_map_queues()
209 amdgpu_ring_write(kiq_rin in gfx_v9_4_3_kiq_map_queues()
[all...]
H A Dgfx_v12_0.c296 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v12_0_kiq_set_resources()
297 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx_v12_0_kiq_set_resources()
299 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v12_0_kiq_set_resources()
300 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v12_0_kiq_set_resources()
301 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v12_0_kiq_set_resources()
302 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v12_0_kiq_set_resources()
303 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v12_0_kiq_set_resources()
304 amdgpu_ring_write(kiq_ring, 0); in gfx_v12_0_kiq_set_resources()
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_0_kiq_map_queues()
333 amdgpu_ring_write(kiq_rin in gfx_v12_0_kiq_map_queues()
[all...]

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