Home
last modified time | relevance | path

Searched refs:PIPE_C (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c138 MMIO_D(PIPEDSL(dev_priv, PIPE_C)); in iterate_generic_mmio()
146 MMIO_D(PIPESTAT(dev_priv, PIPE_C)); in iterate_generic_mmio()
150 MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C)); in iterate_generic_mmio()
154 MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C)); in iterate_generic_mmio()
158 MMIO_D(CURCNTR(dev_priv, PIPE_C)); in iterate_generic_mmio()
161 MMIO_D(CURPOS(dev_priv, PIPE_C)); in iterate_generic_mmio()
164 MMIO_D(CURBASE(dev_priv, PIPE_C)); in iterate_generic_mmio()
167 MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_C)); in iterate_generic_mmio()
193 MMIO_D(DSPCNTR(dev_priv, PIPE_C)); in iterate_generic_mmio()
194 MMIO_D(DSPADDR(dev_priv, PIPE_C)); in iterate_generic_mmio()
[all...]
/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c770 .active_pipes = BIT(PIPE_C),
772 [PIPE_C] = BIT(DBUF_S2),
776 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
779 [PIPE_C] = BIT(DBUF_S2),
783 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
786 [PIPE_C] = BIT(DBUF_S2),
790 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
794 [PIPE_C] = BIT(DBUF_S2),
833 .active_pipes = BIT(PIPE_C),
835 [PIPE_C]
[all...]
H A Dintel_display_limits.h19 PIPE_C, enumerator
36 TRANSCODER_C = PIPE_C,
H A Dintel_display_device.c183 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
190 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
197 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
504 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
581 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
634 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
654 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
678 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
828 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
903 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all...]
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
473 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
576 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
789 .irq_pipe_mask = BIT(PIPE_C),
940 .irq_pipe_mask = BIT(PIPE_C),
1083 .irq_pipe_mask = BIT(PIPE_C),
1178 .irq_pipe_mask = BIT(PIPE_C),
1352 .irq_pipe_mask = BIT(PIPE_C),
1509 .irq_pipe_mask = BIT(PIPE_C),
[all...]
H A Dintel_fdi.c150 crtc = intel_crtc_for_pipe(display, PIPE_C); in intel_fdi_add_affected_crtcs()
227 other_crtc = intel_crtc_for_pipe(display, PIPE_C); in ilk_check_fdi_lanes()
240 case PIPE_C: in ilk_check_fdi_lanes()
429 intel_de_read(display, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
457 case PIPE_C: in ivb_update_fdi_bc_bifurcation()
H A Di9xx_wm.c296 case PIPE_C: in vlv_get_fifo_size()
871 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
872 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
874 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
875 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
878 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
879 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
880 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1751 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; in _vlv_compute_pipe_wm()
1923 case PIPE_C in vlv_atomic_update_fifo()
[all...]
H A Dintel_pipe_crc.c183 case PIPE_C: in vlv_pipe_crc_ctl_reg()
244 case PIPE_C: in vlv_undo_pipe_scramble_reset()
H A Dintel_dmc.c475 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) in adlp_pipedmc_clock_gating_wa()
670 return pipe >= PIPE_C; in need_pipedmc_load_mmio()
703 return pipe >= PIPE_C; in need_pipedmc_load_mmio()
869 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | in intel_dmc_load_program()
H A Dintel_display_irq.c549 case PIPE_C: in i9xx_pipestat_irq_ack()
715 case PIPE_C: in ivb_err_int_pipe_fault_mask()
1291 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
1767 case PIPE_C: in vlv_dpinvgtt_pipe_fault_mask()
H A Dintel_dpio_phy.c696 case PIPE_C: in vlv_pipe_to_phy()
708 case PIPE_C: in vlv_pipe_to_channel()
H A Dg4x_hdmi.c753 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
H A Dicl_dsi.c825 case PIPE_C: in gen11_dsi_configure_transcoder()
1725 *pipe = PIPE_C; in gen11_dsi_get_hw_state()
H A Dskl_universal_plane.c2451 if (DISPLAY_VER(display) == 9 && pipe == PIPE_C) in skl_plane_has_planar()
2717 return pipe != PIPE_C && in skl_plane_has_rc_ccs()
2737 return pipe != PIPE_C; in glk_plane_has_rc_ccs()
H A Dintel_cursor.c529 if (display->platform.cherryview && pipe == PIPE_C && in i9xx_check_cursor()
H A Dg4x_dp.c1377 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
H A Dintel_display_power_well.c1529 assert_pll_disabled(display, PIPE_C); in chv_dpio_cmn_power_well_disable()
H A Dintel_display.c2723 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_transcoder_timings()
3439 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); in joiner_pipes()
3441 pipes = BIT(PIPE_B) | BIT(PIPE_C); in joiner_pipes()
3765 trans_pipe = PIPE_C; in hsw_enabled_transcoders()
H A Dvlv_dsi.c992 if (drm_WARN_ON(display->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
H A Dintel_ddi.c566 case PIPE_C: in intel_ddi_transcoder_func_reg_val_get()
836 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c908 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
911 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
914 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
1022 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
1046 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
2308 MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2309 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2317 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2318 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2339 MMIO_DH(FDI_RX_IIR(PIPE_C), D_AL in init_generic_mmio_info()
[all...]
H A Dinterrupt.c510 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
H A Dcmd_parser.c1297 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1298 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1357 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
1372 info->pipe = PIPE_C; in skl_decode_mi_display_flip()