1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #include "gpu.h" 6 7 #include <engine/fifo/priv.h> 8 9 #include <nvif/class.h> 10 11 const struct nvkm_rm_gpu 12 tu1xx_gpu = { 13 .disp.class = { 14 .root = TU102_DISP, 15 .caps = GV100_DISP_CAPS, 16 .core = TU102_DISP_CORE_CHANNEL_DMA, 17 .wndw = TU102_DISP_WINDOW_CHANNEL_DMA, 18 .wimm = TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 19 .curs = TU102_DISP_CURSOR, 20 }, 21 22 .usermode.class = TURING_USERMODE_A, 23 24 .fifo.chan = { 25 .class = TURING_CHANNEL_GPFIFO_A, 26 .doorbell_handle = tu102_chan_doorbell_handle, 27 }, 28 29 .ce.class = TURING_DMA_COPY_A, 30 .gr.class = { 31 .i2m = KEPLER_INLINE_TO_MEMORY_B, 32 .twod = FERMI_TWOD_A, 33 .threed = TURING_A, 34 .compute = TURING_COMPUTE_A, 35 }, 36 .nvdec.class = NVC4B0_VIDEO_DECODER, 37 .nvenc.class = NVC4B7_VIDEO_ENCODER, 38 }; 39