Searched refs:NUM_DPPCLK_DPM_LEVELS (Results 1 – 12 of 12) sorted by relevance
101 #define NUM_DPPCLK_DPM_LEVELS 8 macro 124 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];153 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
105 #define NUM_DPPCLK_DPM_LEVELS 8 macro 124 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
106 #define NUM_DPPCLK_DPM_LEVELS 8 macro 125 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
105 #define NUM_DPPCLK_DPM_LEVELS 7 macro 130 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
36 #define NUM_DPPCLK_DPM_LEVELS 8 macro 1147 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz1632 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz
34 #define NUM_DPPCLK_DPM_LEVELS 4 macro 72 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
34 #define NUM_DPPCLK_DPM_LEVELS 8 macro 80 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
515 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn316_clk_mgr_helper_populate_bw_params()
107 #define NUM_DPPCLK_DPM_LEVELS 8 macro 133 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
52 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
640 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params() 704 bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS); in dcn314_clk_mgr_helper_populate_bw_params()
943 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn35_clk_mgr_helper_populate_bw_params() 1014 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS); in dcn35_clk_mgr_helper_populate_bw_params() 1215 for (i = 0; i < NUM_DPPCLK_DPM_LEVELS; i++) in translate_to_DpmClocks_t_dcn35()